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  1. K

    What is the defering in ethernet?

    hi can anyone tell me w is defering in ethernet & w is the meaning of like 1/3, 2/3 time regards krishna
  2. K

    code for reversing bits verilog

    reverse bit order verilog thanks Mittal
  3. K

    code for reversing bits verilog

    verilog bit reverse Hi i have tried with all those things. It gives illegal part select error. have u tried with that code? or just putting here module reverse_bits(); reg [3:0] tmp; reg [0:3] data; initial begin data=4'b1010; tmp[3:0]=data[0:3]; //if it is tmp [0:3] it says illegal...
  4. K

    code for reversing bits verilog

    verilog reverse bit order HI Can anyone know how to reverse bits in verilog. The code should be simpler (no functions pls and it should be min lines) bye Added after 1 hours 8 minutes: and this is what i wrote case (m) 0: begin tmp0[0] =...
  5. K

    Solution to interview question about coding

    interview question In simulation it will have problem only when selection line is "X". Otherwise there is no difference after synthesis, whether you implement with ternary or if/else?
  6. K

    What is the setup and hold time?

    setup hold checks The time [before the active clock edge] after which any change in the input data could result in the FF latching the wrong value is characterized as the SETUP time of that DFF. The time [after the active clock edge] for which the DFF output maintains its value before...
  7. K

    Obtaining sweep with a DC level using sweep generator

    Sweep generator plz check with this Added after 17 seconds: https://www.ecircuitcenter.com/Circuits/opsum/opsum.htm
  8. K

    Problem with Opera on RHEL

    Hi, I am using opera in rhel, whenever i am opening opera the following error comes. pls can anyone help me
  9. K

    Some queries referring to RHEL5 (Linux)

    some queries reg RHEL5 hi i am new to linux and i want to know answers to the following 1. how to change monitor frequency like in windows we do my monitor only the 2 freq.s 50 hzs and 60 but in windows they r ranging from 60 to 100 hz 2. how to restore and can we create restore points like...
  10. K

    What does inter frame gap in ethernet contain?

    Re: ethernet hi i dont want the burst duration time or what a sfd contains i want to know what should we send in inter frame gap. special bits ? or something else ? and should i send only in the first frame or in successive frames
  11. K

    What's the difference between fork join and nonblocking statements ?

    hi can anyone tell diff between fork ... join and nonblocking statements in language point of view
  12. K

    What does inter frame gap in ethernet contain?

    hi can anyone tell me what does inter frame gap contains. some special bits or all 1's and is it applied only for first frame in burst cycle or to all succissive frames
  13. K

    Native testbench and System Verilog

    Re: **SYSTEM VERILOG** is anyone having sv assertions by vijayaraghavan
  14. K

    Whats the use of pre_randomize() and post_randomize() ?

    hi whats the use of pre_randomize(), post_randomize() and can any one give example how to use them
  15. K

    what is segmentation fault

    the following code is giving runtime error as "segmentation fault".why? char *str; fp=fopen("f1.txt","r"); fgets(str,10,fp); puts(str); but the following code is working................................................. char *str; fp=fopen("f1.txt","r"); fgets(str,10,fp); for(i=0;i<10;i++)...
  16. K

    problem in return double pointer

    return double pointer how to retern a double pointer from a function.y the following code is not working.. char **func(void); main() { char **ch; ch=func(); prinyf("%s%s",ch[0],ch[1]); } char **func() { char *p[2]={"a","b"}; char **k; k=p; return(k); }
  17. K

    systemverilog websites

    https://www.asic-world.com/ https://www.doulos.com/ the above two sites are having good material for beginers https://verificationguild.com/ https://www.accellera.org/ https://www.systemverilog.org/ https://www.sunburst-design.com/ https://www.sutherland-hdl.com/...
  18. K

    System C & system Verilog

    systemverilog for verification by chris spear and ieee manual (it is available in edaboard) are good material for beginers
  19. K

    systemverilog assertions

    sv +assertions Dear Ajeetha, I am not working in any comp. i want to know is it possible to verify a project completely by using only SVA'S.
  20. K

    systemverilog assertions

    sv assertions hi I know the basics of SV. I am having a doubt, is it enough to learn SV ASSERTIONS to do a complete full project (verifying) or should i learn the whole SV like classes, interfaces, random constraints and so on. thanks in advance

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