Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
How we can write a setup or hold time constraints for a clock that isn't a global clock, it's come from a combinational logic inside my code ?
Take in mind that the tool gives me an error that the this net isn't connected to a pad or a pin when i type the constraints as shown:
Can we apply XDC "Xilinx design constraints" file -which is nearly similar to SDC "Synopsys Design Constraints" in syntax and commands- to XST "Xilinx Synthesis Tool" in ISE, instead of applying the XCF "Xilinx Constraints File" or the UCF files ?
In case the answer is no, So When can we...