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  1. H

    SystemC , Systemverilog , vera , specman...

    i don't know why someone said "systemVerilog is slow", from general understanding, using any third party EDA tool will make the simulator slow. But if we use systemVerilog we don't need any third-party tool through PLI interface. so, using systemVerilog is faster. is my understanding correct?
  2. H

    how to start to learn Synopsys Design Compiler?

    synopsys dc manual attend the synopsys course "chip synthsis workshop", it is pretty good to start from.
  3. H

    The explanation of false paths

    Re: false path In Synopsys Design compiler, a false path is a path for which you will ignore timing constraints. for example, when crossing different asynchronous clock domains. Under this situation, you will have to disable the timing-based synthesis on this path.

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