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  1. H

    an altera stratix device question

    hi, all: in altera stratix fpga device, is the relation between Pin number and I/O bank number fixed? can we program it? in another word, if the pin location has been fixed, do we have the flexibility to connect it to wanted I/O banks? thanks harry
  2. H

    stratix Enhanced /Fast PLL, Gclk, Rclk question

    hi, I am new to stratix FPGA design, maybe my question is too simple. what is the relation between Enhanced/Fast PLL and Global/Regional clock? our current design uses a lot of clocks, and the Global clock number are not enough, so we need to use Regional clocks, but the pin locations have been...

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