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    Why does Design Compiler increase area when using a generate statement with condition

    I am using a generate statement to instantiate a module which is causing an unexplained increase in are after DC synthesis. I am using Verilog The first snippet of code gives me a certain area generate module_name instance name endgenerate I also get the same area if I don't use the...
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    LVS using netlist from Encounter

    I am trying to run LVS using a design I created in Encounter but am receiving a number of errors. I have used the >saveNetlist -excludeLeafCells -includePowerGround command to create a netlist which includes VDD and VSS just like the layout. My standard cells also include VBP and VBN pins...
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    How to solve MinCut DRC violation

    When routing a design with Encounter, I am getting a significant amount of MinCut violations when I verify geometry. They all occur on the same layer. How can I increase the number of cuts used? The MinCut is 3 yet the actual value is 1? Can this be fixed easily?
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    Back annotating SDF - Sum of two annotated limits are less than zero

    I got this warning when back annotating an sdf file. What exactly does it mean and will it cause any problems? ncelab: *W,SDFNL2 (,35120|7): The sum of the two annotated limits to $setuphold, $recovery or $recrem timing checks are less than zero for instance :UUTreg[6] , setting negative...
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    Noise libraries for noise analysis

    I am trying to run noise analysis and need noise libraries which are in the .cdB format as far as I am aware. I only have .lib and .lef library files. Is there a way of converting these. I know there is a make_cdb command but this seems to be for netlists and individual cells. Is there a way of...
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    Using I/O assignment file and instantiating PADs in RTL.

    I am trying to create an I/O assignment file to define the locations of my I/O pads. I don't have any PADs defined yet so I understand I should do this at RTL level in a top-level file. My question is how do I know what cells to instantiate in my VHDL file? Do I use one of the PADs from the IO...
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    Creating a tech file from .ict file.

    I have a .ict file and I need to create a .CapTbl file and a .tch file. I can generate the .CapTbl file using the generateCapTbl command in encounter. Is there a similar command to generate a .tch file as well. I also have a qrcTechFile (with no extension). Should I be using this instead?
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    Where can I find or generate a .captbl file?

    I'm running a synthesis using RTL Compiler and I need a captbl file for physical synthesis for the interconnect RC extraction models. I can find .ict files but I don't have a .captbl file. How can I create one of these or which software do I use?
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    Can block abstraction models and ILMs be used to instantiate multiple instances?

    In IC Compoielr, can block abstraction models and ILMs be used to instantiate multiple instances of a design that has already been routed? Or do these only relate to interface logic. I have a small routed design which has been synthesized from VHDL. How can I create an array of these and make...
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    Can I create an IP block for reuse?

    I have Placed and Routed a small design using Synopsys IC Compiler and would like to use this exact design again as part of a larger design. Is it possible to package it up at make it as an IP block so that I can just instantiate it in a larger design? Do I create a library with this component...
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    Differences in route/zroute

    What is the difference between the two routing methods? Why do some designs route with the classic router but not with the zrouter?
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    Can I P&R the same module multiple times?

    In IC Compiler, using RTL synthesis, is it possible to place and route multiple instances of the same module without flattening the entire large design and P&R the entire design individually?Something like the keep_hierarchy option in the top level VHDL module?
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    How to Implement a repetitive design?

    I have a RTL design (from VHDL) which has been synthesized and routed using IC Compiler. I want to include multiple instances of this design which has already been routed successfully. Rather than including a top level VHDL module which instantiates multiple instances and then routes the entire...
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    Routing with hard macros

    I have a small design which includes a macro RAM block and am trying to perform the Place and Route in IC Compiler. Is there any particular guidelines that I need to follow. I create a floorplan and then fix the RAM macro which seems to be required before doing the placement. When I perform...
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    Zroute and Classic route

    Can anyone explain the difference between Zroute and Classic routing (beside speed) and why they seem to produce different results. Is there a particular reason for when Zroute should be used (eg 65nm etc)?
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    Routin problem using Classic route and Zroutei

    Routing problem using Classic route and Zroute I have a small design which includes a macro RAM block and am trying to perform the Place and Route in IC Compiler. Is there any particular guidelines that I need to follow. I create a floorplan and then fix the RAM macro which seems to be required...
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    Macro Place and Route

    I have a small design which includes a macro RAM block and am trying to perform the Place and Route in IC Compiler. Is there any particular guidelines that I need to follow. I create a floorplan and then fix the RAM macro which seems to be required before doing the placement. When I perform...
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    Routing a design using route/zrt in IC Compiler

    I am routing a design in IC Compiler. From what I understand, ZRoute is a newer faster method of routing a design. If I use this method route_zrt_auto, is it then possible to do optimizations using the route_opt command if I use the -skip_initial_routing switch? I am just slightly confused as...
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    [SOLVED] Creating Milkyway library with macro .lef file

    I am trying to create a Milkyway library which includes the physical library for a RAM macro. I have the .lef file from the RAM. Can I do this from the Design Vision tool using the create_mw_lib command or will I have to do it from the Milkyway Environment. I am currently creating the Milkyway...
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    Adding RAM macro physical library to design

    Hi, I am using a hard macro in my design (RAM) and I have added the .db file (converted from .lib) to the link_library for synthesis. I am running Design Vision in topographical mode so I will also have to include a physical library for my RAM macro. I already have a .lef file which I...

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