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    VMware Linux CentOS Cadence memory RAM limitation

    Thanks for your reply Yes, my system is 64bit. The OS (windows) on my computer is win 10 64bit. But, I'm running CentOS on VMware. And I didn't understand your second question "What uname -a says?"? Thanks
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    VMware Linux CentOS Cadence memory RAM limitation

    Hi everyone, I'm a IC desiner. I am using VMware Workstation to run CentOS and Cadence in its environment. I have promoted my PC memory Ram to 12 GB and allocate 9.7 GB to CentOS by VMware. However, when I open the Terminal in CentOS and run the "$ free -m" code in it, the memory info in CentOS...
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    source coudn't be read

    Thank you for replying I don't understand it's a solution way or it's not solution. At all, i don't understand his way and i don't know how he has resolved it. If it's a solution, can you tell me about the proposed way to run LVS without any problem???
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    source coudn't be read

    Hi guys i run LVS with calibre and get an error as shown in image attachment. But when i change nmos_rf to nch, RVE window show match message. Also i saw a same problem in this link: https://groups.google.com/forum/#!topic/comp.cad.cadence/_VSwC51pkOk but i don't understand what it says or...
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    90nm calibre LVS error

    Thank you for replying. But i get this error. It says not compared. Is this error for LVS option settings???
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    90nm calibre LVS error

    Hi guys I drew an LNA layout. I got DRC with *.DN.* and CSR.* error & ignored them. But now, when i want to take LVS, i get "Source could not be raed" error as shown in the picture that it has attached to this message. You can see input option settings in the second picture i attached. How can i...
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    [SOLVED] 90nm calibre DRC error

    Thank you very much. It solved :smile::smile::wink::wink:
  8. A

    [SOLVED] 90nm calibre DRC error

    Hi guys I'm using TSMC90nm and calibre. When I draw a path with 45-degree, i get grid error in calibre DRC. The error is on picture that attach to this message. If i use 45-degree path, i get this error. Also the snap spacing has true value. How can i resolve it???
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    Calibre menu doesn't appear

    Hi guys I'm an RF designer with Cadence 5.1 and tsmc 90nm. I designed circuits. But when i want to draw layout, i can't see calibre menu. I xhecked .cdsinit file and there is no problem with loading "calibre.skl". please help me
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    NF of a receiver front end at standard blocker frequency

    I'm using N-path filters. So It's filter and mixer. Therefore I should do pss/pnoise analysis. My RX is direct conversion. So my LO is 2 GHz and I give a 0-dBm blocker. My RX is for GSM. So Blocker offset frequency is 20 MHz. But my PC don't have enough Ram to calculate that. So I give 80 MHz...
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    NF of a receiver front end at standard blocker frequency

    Thanks for your help. I set port properties, But set first sinusoid. Is it wrong? My filters don't attenuate the 80 MHz 0-dBm blocker at the any nodes of receiver when I run tran analysis and I give 80 MHz 0-dBm. But when I see pac plot, signals at 80 MHz are rejected more than 13 dB. My...
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    NF of a receiver front end at standard blocker frequency

    Hi guys. I designed a front end of wideband receiver. I did pss/pnoise analysis to calculate total noise figure of receiver. The pac magnitude at the "small signal params" is 1 and phase is 0. I can see noise figure plot without any problem. But now i wanna to calculate the total noise figure of...
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    SPECTRE RF convergence error pss analysis in an N-path filter combiner design

    Hi everyone I'm designing a wideband receiver with N-path filters. At the last stage we must use combiner to collect the voltages on the capacitors. I have designed combiner with 3-stage inverters. To work properly, I added resistor feedback between first and last stage. But when I run pss...
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    N-path filters & their flicker noise of clock generation

    Hi guys. I'm a master student. I designed a receiver using N-path filters for filtering & mixing input signals. For driving the N-path filter switches, we need to design a clock genefration with 1/N % duty-cycle. But in the total noise of receiver, we observe flicker noise of clock generation...
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    importing folders & files to icfb

    Re: Importing simulations & analysis states to PC No, it's not true. Now I can solve it. I copied the content of "simulation" folder in the lab university data folder to "simulation" folder in the PC home data folder. Also I copied the content of ".artist_states" folder in the lab university...
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    importing folders & files to icfb

    Importing simulations & analysis states to PC Hi everyone. I'm a amateur user in cadence & linux. I had some data from university lab. I added it to my laptop. But states of analysis & simulations are not work. In other word, I copy & paste the university lab data to "simulation" and...
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    importing folders & files to icfb

    Inside of ".artist_states" folder or "simulation" folder?
  18. A

    importing folders & files to icfb

    I use spectre. But in the load state window there is not anything
  19. A

    importing folders & files to icfb

    I find the problem. I copy ".artist_states" from lab data to my PC's ".artist_states" folder. Also I copy simulation folder from lab data to my PC's simulation folder. Now I can find them in the states https://obrazki.elektroda.pl/5739795900_1487962477.jpg But when I was load it, this error is...
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    importing folders & files to icfb

    It's shared from windows. SSSSSSSSShhhhhhhhhhhhaaaaaaaaarrrrrrrrreeeeedddddddd I can use both of data. But I can't use simulation state of university lab data

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