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Thanks for your reply
Yes, my system is 64bit. The OS (windows) on my computer is win 10 64bit. But, I'm running CentOS on VMware.
And I didn't understand your second question "What uname -a says?"?
I'm a IC desiner. I am using VMware Workstation to run CentOS and Cadence in its environment. I have promoted my PC memory Ram to 12 GB and allocate 9.7 GB to CentOS by VMware. However, when I open the Terminal in CentOS and run the "$ free -m" code in it, the memory info in CentOS...
Thank you for replying
I don't understand it's a solution way or it's not solution. At all, i don't understand his way and i don't know how he has resolved it.
If it's a solution, can you tell me about the proposed way to run LVS without any problem???
i run LVS with calibre and get an error as shown in image attachment.
But when i change nmos_rf to nch, RVE window show match message.
Also i saw a same problem in this link:
but i don't understand what it says or...
I drew an LNA layout. I got DRC with *.DN.* and CSR.* error & ignored them.
But now, when i want to take LVS, i get "Source could not be raed" error as shown in the picture that it has attached to this message.
You can see input option settings in the second picture i attached.
How can i...
I'm using TSMC90nm and calibre.
When I draw a path with 45-degree, i get grid error in calibre DRC.
The error is on picture that attach to this message.
If i use 45-degree path, i get this error. Also the snap spacing has true value.
How can i resolve it???
I'm an RF designer with Cadence 5.1 and tsmc 90nm. I designed circuits. But when i want to draw layout, i can't see calibre menu. I xhecked .cdsinit file and there is no problem with loading "calibre.skl".
please help me
I'm using N-path filters. So It's filter and mixer. Therefore I should do pss/pnoise analysis. My RX is direct conversion. So my LO is 2 GHz and I give a 0-dBm blocker. My RX is for GSM. So Blocker offset frequency is 20 MHz. But my PC don't have enough Ram to calculate that. So I give 80 MHz...
Thanks for your help. I set port properties, But set first sinusoid. Is it wrong?
My filters don't attenuate the 80 MHz 0-dBm blocker at the any nodes of receiver when I run tran analysis and I give 80 MHz 0-dBm. But when I see pac plot, signals at 80 MHz are rejected more than 13 dB.
I designed a front end of wideband receiver.
I did pss/pnoise analysis to calculate total noise figure of receiver. The pac magnitude at the "small signal params" is 1 and phase is 0.
I can see noise figure plot without any problem.
But now i wanna to calculate the total noise figure of...
I'm designing a wideband receiver with N-path filters.
At the last stage we must use combiner to collect the voltages on the capacitors.
I have designed combiner with 3-stage inverters. To work properly, I added resistor feedback between first and last stage.
But when I run pss...
I'm a master student. I designed a receiver using N-path filters for filtering & mixing input signals.
For driving the N-path filter switches, we need to design a clock genefration with 1/N % duty-cycle.
But in the total noise of receiver, we observe flicker noise of clock generation...
Re: Importing simulations & analysis states to PC
No, it's not true.
Now I can solve it. I copied the content of "simulation" folder in the lab university data folder to "simulation" folder in the PC home data folder.
Also I copied the content of ".artist_states" folder in the lab university...
Importing simulations & analysis states to PC
I'm a amateur user in cadence & linux. I had some data from university lab. I added it to my laptop. But states of analysis & simulations are not work.
In other word, I copy & paste the university lab data to "simulation" and...
I find the problem. I copy ".artist_states" from lab data to my PC's ".artist_states" folder. Also I copy simulation folder from lab data to my PC's simulation folder. Now I can find them in the states https://obrazki.elektroda.pl/5739795900_1487962477.jpg
But when I was load it, this error is...