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I've faced some problems in synthesis and atpg for 2 scan clocks. My situation is:
1. The top includes other non-scanable blocks such as ROM, analog, test mode entering logic.
2. Scan test mode can be entered only after a specific sequences of 3 pins (T1,T2,T3)
3. Two scan clocks...
About SDRAM's CLK
Hello, I'd like to design the sdram controller. After surveying the current SDRAM frequency, the most common is 100/133MHz. What if my design doesn't run in such high freqency. It's only 60 MHz or 30 Mhz in my design. So can I just use low clock freq into SDRAM module's CLK...