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  1. W

    layout extraction precision

    Hi All, I am using calibre 2010.2_13.12. there is an option in the PEX option-database-presicion, where one can specify precision and resolution. but no unit is given for these two. any one can help to explain how to interpret these two numbers ? thanks in advance. whlinfei
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    RF IC layout inverter signal routing

    Hi all, I am doing the layout for a RF cmos inverter chain. As the inverter gets bigger, the distance between the leftest and rightest finger becomes quite large. around 30um. the circuit operates at around 1.6GHz. Can I connect all the fingers together and route the input signal at the...
  3. W

    transmitter spectral density

    Hi, I have run the transient simulation on a polar modulated transmitter. How I can get the power spectral density of the output signal? thanks in advance. regards, whlinfei
  4. W

    How to generate baseband QPSK signal?

    Hi, Can anyone tell me how to generate baseband QPSK signal in candence? I need a baseband signal to drive my PA. And I don't have access to SPW. Thank you. Best Regards, whlinfei
  5. W

    create a PWL file in cadence

    Hi all, I want to generate a QPSK signal to drive my Power amplifier. Please tell how to generate a PWL as the input signal. Thanks. Best Regards, whlinfei
  6. W

    gate associated capacitance

    Hi all, Can anyone tell me how to get the gate associated capacitance? I tried DC operating point, but I don't know what those parameters stand for. Is there any other ways I can get the gate related cap? Thanks in advance. Best Regards, whlinfei
  7. W

    questions about RF power amplifiers and non-constant envelope signals

    Hi, I am using a QPSK modulation. Based on the literature I have gone through, it is supposed to be a non-constant envelope due to filtering. So I have to use a linear RFPA to amplifier the signal. I am curious that since the envelope variance is caused by phase change only, why can't I just...
  8. W

    Cartesian to Polar Transform

    Hi all, Can anyone provide some insight into digital transform of Cartesian to Polar ? I understand the transform algorithm Cordic. But I am not sure how the digital architecture is used to implement it ? I would like to construct a matlab model for it. thank you. Best Regards, whlinfei
  9. W

    some questions on QPSK and transmitters

    Hi, I am doing Power amplifier design. In many PA papers, QPSK is considered as a non-constant envelope signal. But from its waveform, it seems it's constant-envelope. Some books say the filtered QPSK is non-constant envelope. Even in that case, how is the signal demodulated given that the...
  10. W

    RFPA : drain to source breakdown voltage

    Hi All, Does anyone use Chatered 65nm process, CH65LPe ? I couldn't find the drain to source breakdown voltage for I/O FET. The highest nominal Vdd is 2.5V. Burn in is around 3.8. But for PA design, the maximum drain to source voltage is above 2 times Vdd. Please help. Best Regards, whLinfei
  11. W

    Class E RF power amplifiers input signal

    Hi All, I've been checking class E amplifier literatures, but couldn't find anything mentioning how to generate the input signal. Normally, only a 50% duty cycle is presented to explain circuit operation. My application is based on CDMA, QKSK. So how do I use the I and Q to get my input signal...
  12. W

    RFPA design simulation PSS Vesus QPSS

    Hi, I am trying to simulate RFPA using spetreRF. I understand that there are two PSS simulation method. PSS and QPSS. since QPSS does not assume of periodicity, does it mean that it is more accurate than PSS? Thanks. Best Regards, whlinfei
  13. W

    DFT in cadence spectre

    Hi all, I am trying to use DFT to get the THD of my design. But somehow the output waveform give only a input frequency component and some of its harmonics with the same magnitude. ( I used Hspice to verify that the DFT result should not be like that.) can anyone tell me how to fix it ...
  14. W

    RF power amplifier design simulation

    Hi All, I have just finished a RFPA design using Cadence. For a typical RFPA design, what simulations do I have to run to get some standard parameters? Like IP3, spectral regrowth, maximum output power all that? Thank you. Best Regards, whlinfei
  15. W

    simulink/Matlab simulation of a transceiver design

    Hi All, I am doing the 1st version of a transceiver design. The plan was to do a system simulation using matlab/simulink so that I can understand the parameters for each individual blocks before I start building the actual circuits. Is there any materials I can base on for a first timer in RF...
  16. W

    FFT in cadence testing PSRR

    Hi all, I am trying to inject a small sine wave at the supply(Vdd) to test the circuit's supply supply rejection ratio. the method I use is to inject a 1.5k sine wave at the Vdd. and the input signal is 1k. ideally if I use fft, I should see a large 1k frequency component and a small 1.5k...
  17. W

    mixed signal ESD protection

    Hi All, I am designing a Class D amplifier with three power domains,namely power, digital and analog. Now I am at the stage of drawing the layout for pads and esd protections. I see normally there is ESD Vdd and ESD ground for connection of input esd diodes. But that will degrade the noise...
  18. W

    bandgap start up testing and consideration

    Hi All, I have a bandgap reference circuit, which works fine in simulation. (Both DC temperature sweep and transient sweep give satisfactory results.) As this is my first fabrication, I am a bit concerned about the start-up and also the stability of the circuits. startup the startup circuit...
  19. W

    Rules for contact redundancy when drawing the layout using CMOS process

    Hi All, I am drawing the layout using a cmos process. I am a bit concerned on "contact redundancy ". It is better to put as many contacts as possible. But is there any minimum number of contacts to place for a connection? what is the rule to follow there ? say I have a gate connection ? how...
  20. W

    calibre error another cell record encountered for cell

    calibre LVS errors Hi All, LVS gave the following error messages. Clearly it can identify the resistors both in schematic and in layout. But somehow it refuses to match these two to be the same. Can anyone help me on that? thanks. Whlinfei INCORRECT...

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