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I am using calibre 2010.2_13.12.
there is an option in the PEX option-database-presicion, where one can specify precision and resolution.
but no unit is given for these two.
any one can help to explain how to interpret these two numbers ?
thanks in advance.
I am doing the layout for a RF cmos inverter chain.
As the inverter gets bigger, the distance between the leftest and rightest finger becomes quite large. around 30um.
the circuit operates at around 1.6GHz.
Can I connect all the fingers together and route the input signal at the...
Can anyone tell me how to get the gate associated capacitance?
I tried DC operating point, but I don't know what those parameters stand for.
Is there any other ways I can get the gate related cap?
Thanks in advance.
I am using a QPSK modulation. Based on the literature I have gone through, it is supposed to be a non-constant envelope due to filtering. So I have to use a linear RFPA to amplifier the signal.
I am curious that since the envelope variance is caused by phase change only, why can't I just...
Can anyone provide some insight into digital transform of Cartesian to Polar ?
I understand the transform algorithm Cordic. But I am not sure how the digital architecture is used to implement it ?
I would like to construct a matlab model for it.
I am doing Power amplifier design.
In many PA papers, QPSK is considered as a non-constant envelope signal.
But from its waveform, it seems it's constant-envelope.
Some books say the filtered QPSK is non-constant envelope.
Even in that case, how is the signal demodulated given that the...
Does anyone use Chatered 65nm process, CH65LPe ?
I couldn't find the drain to source breakdown voltage for I/O FET.
The highest nominal Vdd is 2.5V. Burn in is around 3.8. But for PA design, the maximum drain to source voltage is above 2 times Vdd.
I've been checking class E amplifier literatures, but couldn't find anything mentioning how to generate the input signal.
Normally, only a 50% duty cycle is presented to explain circuit operation.
My application is based on CDMA, QKSK. So how do I use the I and Q to get my input signal...
I am trying to simulate RFPA using spetreRF.
I understand that there are two PSS simulation method. PSS and QPSS.
since QPSS does not assume of periodicity, does it mean that it is more accurate than PSS?
I am trying to use DFT to get the THD of my design.
But somehow the output waveform give only a input frequency component and some of its harmonics with the same magnitude. ( I used Hspice to verify that the DFT result should not be like that.)
can anyone tell me how to fix it ...
I have just finished a RFPA design using Cadence.
For a typical RFPA design, what simulations do I have to run to get some standard parameters?
Like IP3, spectral regrowth, maximum output power all that?
I am doing the 1st version of a transceiver design.
The plan was to do a system simulation using matlab/simulink so that I can understand the parameters for each individual blocks before I start building the actual circuits.
Is there any materials I can base on for a first timer in RF...
I am trying to inject a small sine wave at the supply(Vdd) to test the circuit's supply supply rejection ratio.
the method I use is to inject a 1.5k sine wave at the Vdd. and the input signal is 1k. ideally if I use fft, I should see a large 1k frequency component and a small 1.5k...
I am designing a Class D amplifier with three power domains,namely power, digital and analog.
Now I am at the stage of drawing the layout for pads and esd protections.
I see normally there is ESD Vdd and ESD ground for connection of input esd diodes.
But that will degrade the noise...
I have a bandgap reference circuit, which works fine in simulation. (Both DC temperature sweep and transient sweep give satisfactory results.)
As this is my first fabrication, I am a bit concerned about the start-up and also the stability of the circuits.
the startup circuit...
I am drawing the layout using a cmos process.
I am a bit concerned on "contact redundancy ".
It is better to put as many contacts as possible. But is there any minimum number of contacts to place for a connection? what is the rule to follow there ?
say I have a gate connection ? how...
calibre LVS errors
LVS gave the following error messages.
Clearly it can identify the resistors both in schematic and in layout.
But somehow it refuses to match these two to be the same.
Can anyone help me on that?