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physical significance of zeros and poles
this has been always a matter of confusion to me whenever i sit and think about poles and zeros. And still after reading all above discussions......i think somewhere, something is missing.....
Is it just mathematics...
I think its better to use Nmos op amp. but depending on situation like whats the input common mode ...we need to decide which will be best in terms of OVD and SAT margins. Second stage must be a gain stage and NMOS always has adv of smaller size (so smaller parasitics) over Pmos counter part.
i think there might be some mistake when u r breaking the loop for stability analysis. Can u post ur cir file in which u r doing this.. then probaly i may help u.
Ur dc operating point of circuit should not change when u r doing an AC analysis. what r u doing for this ???
AC = 1 volts eases the computation.
Gain = vout/vin and u can see when u write vdb(vout) it gives u gain (Vout/vin) at that node. It does not affect any other thing. u can write whatever u want here but in that case u have to see how can u extract gain from the simulator u r using???
Its absurd to make u learn all those things. Now a days where there are concepts of open book exams r growing up, these is abosultely rubbish.
But my frnd at some places its like that only. so just see the prev Q paper and learn the imp thngs only. So that u can get good marks...
VHDL to LAYOUT
U r right. Cadence can give me a layout from vhdl. But i dont have that tool in the lab. so i was looking for an alternative. Also as u have said i can do in tanner too using hierarchy but surely that will consume more time. It was my minor project only so i...
VHDL to LAYOUT
thanks for the suggestions frnds. I have the ISE 7.1 tools in my institute lab so that is not a problem, the problem is to generate a layout as we do in cadence and t spice etc. So how that can be generated from VHDL code. There is a tool in cadence that can genrate this...
I ve encoutered one problem while programming xilinx FPGA kit. It shows cable is not connected. when i do autodetect cable it shows cable is connected but when i say program then again it says that cable isnot connected.
what cud be the problem???
help, i m new to it.
NO one has mentioned the famous book fo digital ciruits and design.
Added after 2 minutes:
forgot to mention.
for VLSI technology--S M Sze
digital cmos intgated ckts-kang and leblebici
also one book is on digital design by Wayner wolf
at VDD-VTN , for nmos swiched, Ron goes to infinity, its normal. U can see the expression for Ron. For Vin = Vdd-Vtn expression has zero in denominator so Ron is infinity.
Is this what ur quiestion is??????
VHDL to LAYOUT
But i want to know whether this site gives us the free tools to do our work(if i m getting the tool which serves my purpose).
Can u tell me in detail if u know more????
Can it really offers some tool which can convert the vhdl code to a netlist which can...
If want to study mosfets in deep and have some analysis of them at circuit as well as device level. here is one good book
CMOS Digital Integrated Circuits Analysis & Design - by Sung-Mo (Steve) Kang, Yusuf Leblebici
for analog cmos ciruits.
Analog CMOS circuits be Behzad razavi is good one.