Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
We got a strange bode plot for a constant on time DC-DC Buck converter. This converter shows the phase crosses the zero line at low frequency. This attached waveform is the simulation results of Simplis. the network analyzer shown the similar result. Both transient simulation and test...
OK, it is a big question. Let me try to answer it.
1. It's important to the whole transfer function of the power stage and will determin the compensation design. (Bandwidth is directly related to transient response)
2. The ESR will help the stability but will generate more ripple. For old...
Acturally, I cannot fully understand the circuit. especially about the second differential pair. Could you tell me the function of that? Looks like you have a lot of amplifier stages, which can easily cause stability problems.
What I noticed is the way you did AC...
lm10 band gap calculation
I want to understand the bandgap circuit used in lm10, which is designed by Widlar in 70s. But it's not so easy. I upload the simplified circuit here. Hope you can help me. The circuit is below,
Thanks a lot
High frequency makes the current ripple on inductor and the voltage ripple on capacitor smaller. So, smaller L/C can be used to achieve same ripple.
With high frequency, the control bandwidth can also be pushed to higher frequency, the compensation compensation can be smaller, too.
monostable in verilog-a
I find the absdelay statement.
The VerilogA program is list below, in case someone may need it. Thanks,
// VerilogA for PMM_VA_Models, mono, veriloga
module mono(vin, vout);
electrical vin, vout, vindelay...