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  1. achaleus

    CDC for constant signal

    Even if condition is changing start_reading is always high irrespective of condition after initial assignment
  2. achaleus

    CDC for constant signal

    always @ (posedge clk_153) begin if (reset) start_reading <= 1'b0 ; else begin if(condition1) // once this condition occur start_reading is always high start_reading <= 1'b1 ; end end always @ (posedge clk_102) begin if (reset) read/_en <=...
  3. achaleus

    What is the exact use of Wrapping burst transactions in AXI 4 ?

    Dear EDA Board members, let us take one example with Burst Length=8, Number of Bytes=4 and Starting address=0x4a and data needs to be transferred using Wrapping Burst. I have calculated the address of each transfer with respect to equations given in AMBA AXI Protocol Version 2.0 Specification...
  4. achaleus

    Anti aliasing in VIPT cache

    Dear edaboard, While designing a cache we should satisfy the condition cache size <= BLOCK size * set associativity, if we increase cache size or by decreasing associativity we ran into aliasing problem. there are very less information available regarding overcoming aliasing (anti aliasing...
  5. achaleus

    C library call from assembly generated by gcc from some c code

    Re: c library call from assembly generated by gcc from some c code I have done single step gdb debugging, #addsd %xmm1, %xmm0 # commented actual addition call add # added my library call here movsd %xmm0, (%rax) # segmentation fault here
  6. achaleus

    C library call from assembly generated by gcc from some c code

    The assembly of add.c is given below, where it is operating on %xmm0 and %xmm1, and in actual assembly this add call should actually work . gcc -c add.c ar -crv libtemp.a add.o gcc -S exp1.s -ltemp L. exp1.o gcc exp1.o -o exp1 -ltemp L. ./exp1 -- segmentation fault .file "add.c"...
  7. achaleus

    C library call from assembly generated by gcc from some c code

    I am experimenting on modifying assembly by calling c library from assembly, I ran into segmentation fault exp1.c contains #include <stdio.h> double *a,*b,*c; int main() { double a_d = 1.1; double b_d = 2.1; double c_d; c = &c_d; a = &a_d; b = &b_d; *c = (*a + *b); printf("\n%lf",*c); }...
  8. achaleus

    -msoft-float -m64 x86 machine, gcc is not referring to software floating point librar

    Dear edaboard, I have a third party software floating point library which was compiled using 64 bit machine (-m64). I am trying to infer this floating point library using gcc flag -msoft-float. If I am using gcc -msoft-float -m32 flag for c = a+b, where c,a,b are float values,gcc infers...
  9. achaleus

    [SOLVED] timing problem in doing CLOCK DOMAIN CROSSING

    with TIG, it simply ignores the timing for all those paths with cdc even if it is not meeting (considering all those paths which are failing), so I don't know whether that is an efficient way. I didn't get why you have written 3*4
  10. achaleus

    How can I monitor a signal in post synthesis .v file

    Hello ads-ee (* KEEP = "TRUE" *) works for hierarchy also.. though I have taken that signal top to the hierarchy and kept as output.. but it is giving error as Unresolved reference.
  11. achaleus

    How can I monitor a signal in post synthesis .v file

    Thank you dpaul and ads-ee for solutions. I used keep = TRUE attribute and pinned to the top level in the hierarchy. and used $monitor("current iteration is %d",PicoSim.FPGA.UserWrapper.UserModuleTop.my_iteration1 ); but I got Unresolved reference to 'my_iteration1' in...
  12. achaleus

    How can I monitor a signal in post synthesis .v file

    I thought the same and kept it as my final option... thank you dpaul
  13. achaleus

    How can I monitor a signal in post synthesis .v file

    Hello everyone, I am using ISE 14.7 for synthesis and Questasim 10.0c for simulation. I am doing post synthesis simulation to find out simulation and synthesis mismatch. ISE elaborated all hierarchy files into a single file for e.g. \instance1/my_signal[15:0]. The signals generated are so vast...
  14. achaleus

    [SOLVED] timing problem in doing CLOCK DOMAIN CROSSING

    While doing CDC, I am using 3 flop synchronizer from slow clock(100MHz) to fast clock(250MHz). It is reporting timing not met as (I am using xilinx 14.7 for synthesis) Source Clock: clk_100 rising at 10.000ns Destination Clock: user_clk rising at 12.000ns but actually it should report...
  15. achaleus

    Forcing a variable in Modelsim or questasim simulation

    Hello TrickyDicky, we have an option in verilog coding like {256{F}} something like that can we force (error injection or whatever maybe) through wave window
  16. achaleus

    Forcing a variable in Modelsim or questasim simulation

    Hello edaboard, how can I force a variable/signal in modelsim/questasim to all ones. suppose I have a signal with vector length 512 so how can I force to all one's thank you, achaleus
  17. achaleus

    Unable to generate ap_idle as high in Vivado HLS

    Hello edaboard, I have written one module in Vivado HLS, where simulation waveforms are fine. I generated EDIF from Vivado design suite converted to .NGD using ngdbuild and to verilog using netgen tcl commands from xilinx and done simulation using modelsim. There ap_idle is not getting high...
  18. achaleus

    [SOLVED] How to synthesis files taken from Vivado hls

    hey thanks for the reply I am using vivado 2012.2, I implemented this design( taking .zip file generated from Vivado hls) in vivado design suite but I unable to find EDIF. How to generate this EDIF file so that I will use this design as black box in other designs. we have V6 FPGA boards

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