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    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim i got the same result as yours with your do file. :D very nice. will take a look at the do file and hopefully i can use it as a basic for the rest of my future designs. thanks to all for your help, especially walid farid. very much appreciated! regards
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    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim hi, i follow those commands and did not get the same result. mine still shows red and blue lines. can you clarify what you meant by: force the signals using the Modelsim GUI...instead of a testbench. here is how i do mine. maybe i am missing a step somewhere. 1. create...
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    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim hi, i have attached 2 files. one is a design and the other is psl file. please keep in mind that i am not after the design itself as can be seen from the file. what i am after is how to simulate the design with a psl file as oppose to the a regular testbench. so...
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    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim i got it working with psl using modelsim. but now i got another problem. when i run the simulation i got nothing but red and blue lines in the wave window. this only happens when using psl. with a regular testbench there is a timing diagram. need to work on this. again...
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    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim walid, if you can please upload them. do you have a step by step process of how to simulate a design with a psl file using Modelsim? the simplest the better as i am very new to this vhdl stuff. :D salma ali bakr, thanks for the heads up. Added after 3 minutes: this is...
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    Where to get a free VHDL software?

    download vhdl software if i understand this right, you want free software to simulate/synthesize the vhdl code? both xilinx and Altera provide free version of their synthesis tool for download. xilinx has their webpack while altera gives you their quartus. for simulation you can download...
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    Looking for materials to learn about vhdl and verilog

    Re: about vhdl, verilog not ebook or free software but i find these links to be useful for self study. hope this help https://www.doulos.com/knowhow/ https://www.fpga4fun.com/ regards
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    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim thank you all for the response. your effort in trying to help is very much appreciated. what i am looking for is an example of a simple design plus external psl file (verification unit file) that i can follow through using modelsim. so basically...two files. 1...
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    How to simulate a design with a psl file using Modelsim?

    Re: PSL file-Modelsim Thanks for your input. Anyone else have any suggestion? Regards
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    How to simulate a design with a psl file using Modelsim?

    modelsim vunit file Hi all, Can some please verify if this is true... For simulation, instead of writing a regular testbench you would write a psl file for your design and use Modelsim to simulate. I am very new to this vhdl stuff and have been doing lots of reading but still confuse :cry...

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