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  1. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    is this the netlist? // Generated for: spectre // Generated on: Jul 1 20:58:47 2017 // Design library name: patruzecisitrei // Design cell name: oscilator // Design view name: schematic simulator lang=spectre global 0 vdd! include "/work/tdk/AMS/H18/4.11/spectre/h18/soac/mcparams.scs" include...
  2. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    Ok so I'm back with cadence unfortunately... so I remade my circuit, I do the tran analysis, its oscillating around 1.2GHz which is great but for some reason I can't do a damn PSS analysis... I keep getting this error for my MOSFET's: ERROR (SPCRTRF-15177): PSS analysis doesn't support...
  3. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    well that's a bit harsh... I'm only seeking advice here... maybe someone else can provide feedback if you don't want to help... thank you for your feedback so far but I think I'll try @Audioguru suggestion and hope for better frequencies...
  4. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    I don't know how to show you the netlist... the width and length of transistors...
  5. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    So I've tried your suggestion and used a step pulse for vdd (1.2V) and got a oscillation frequency of ~16GHz and a phase noise of -68 dBc/Hz... Is this normal? I think there is something wrong... The inverters have 120nM and 100nM each...
  6. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    HAHAHAHAHAHAHAA OMG I've almost died of laughter! I'm far from professional, I'm just a poor student just starting out to learn engineering... there is very much information that I have to assimilate and put together by myself... Anyway I'll try your suggestions from post #6 and come back with...
  7. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    Could you recommend another which can easily approach the periodic analysis?
  8. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    I need to do a PSS analysis to determine the frequency of oscillation and the influence of parameters such as supply voltage, temperature or load capacitance over the oscillation frequency, a transient analysis for the simulation of the circuit and a PNOISE analysis to determine the phase noise...
  9. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    Thanks I'll give it a try... I'll also need to do the PSS and the Phase Noise...can these be approached with LTspice?
  10. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    yeah... I totally forgot about that... anyway Cadence Virtuoso is giving me a headache, its so clunky and I can't even find parts that I see in online tutorials... Can someone recommend a great FREE circuit simulator? One in which I can easily manage the three analysis I've mentioned in post #1.
  11. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    I might have left out the fact that I'm totally dumb when it comes to electronics... I'm a beginner so please don't make fun of me...
  12. C

    How do I simulate a 3 stage Ring Oscillator? [Virtuoso]

    Hello Forum! I need some guidance. Please follow the screenshots in the attachments. So first I made the schematic for the inverter, then I've setup the symbol for it and using that symbol I've quickly put together a 3 stage ring oscillator. I've got here using information found on google...
  13. C

    simulating a IIR filter butterworth method in matlab

    Hello! Can someone point me to some detailed matlab tutorials that can help me with my assignment? Or a few explanations would be much appreciated. IIR filter Butterworth method Fpas s=9kHz, Fstop=11kHz, Apass=1dB, Astop=25dB and Fs=40kHz IIR filter analog prototype H(s)=...
  14. C

    simulating a IIR filter Butterworth method in MATLAB

    Hello! Can someone point me to some detailed matlab tutorials that can help me with my assignment? Or a few explanations would be much appreciated. IIR filter Butterworth method Fpas s=9kHz, Fstop=11kHz, Apass=1dB, Astop=25dB and Fs=40kHz IIR filter analog prototype H(s)=...
  15. C

    verilog combinational code

    ok so what if: C*(!A*!D+A*!B+!A*!B*D) + !C*(B*D+A*!B*!D) for C A0 is !D+!B*D and A1 is !B and for !C A0 is A*!B and A1 is B can someone confirm this?
  16. C

    verilog combinational code

    I tried simulating on iverilog.com but I got an error when trying to assign q = ^in however the other code worked just fine. I just realized that I can't use a mux because the exercise was strictly about a 3:1 combinational circuit with a,b,c as in and q as out... Anyway... does anyone remember...
  17. C

    verilog combinational code

    like this? module ex (in,q); input [2:0] in; output reg q; always @(in) case (in) 3'b000: q=0; 3'b001: q=1; ... endcase
  18. C

    verilog combinational code

    Hello! So I have the next assignment: write a verilog code for a combinational circuit that have the next values: input output 0-0-0 > 0 0-0-1 > 1 0-1-0 > 1 0-1-1 > 0 1-0-0 > 1 1-0-1 > 0 1-1-0 > 0 1-1-1 > 1 can this be done with a 3:1 mux with two selections?
  19. C

    [SOLVED] Connecting two FPGA's together

    Someone pointed out that there could also be a problem about the buffer limit? I'm not sure what he meant... can someone explain?
  20. C

    [SOLVED] Connecting two FPGA's together

    your answer is great but it depends on an unspecified feature of the second FPGA, what if it does have a input tolerance of 5V? What about this case? Could some errors pop up or the two FPGA's would just synergize perfectly?

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