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  1. K

    How do you implement X^2.5???

    I have asked about implemetation of X^2.5 while X is a vector of 8-bit. No alhorith implemetaion is required. I have suggested the following solution: X^2.5= X^2*X^0.5 for X^2 I will use simple multiplier(X*X). X^0.5 I will use ROM. then I will multiply the results.
  2. K

    Looking for documents about ECC memory

    May anyone recommend me on a free core of ECC??? Or at least if you have good DOCs about it.
  3. K

    Using System ID core for Altera Startix-II without NIOS

    I am using Altera'Startix-II with out NIOS. I only using its memory and logic. I want to build a component that holds the version of the current FPGA image. this version is incremented every new version of FPGA so I can read it by Read Only register. I have no flash. In the past, when I used...
  4. K

    How to display fraction in VHDL simulation???

    represent fractions in vhdl how supposed an unsigned vector A_UNS which represent 4.3 in form q.r: 4 : represents 4-bit of the QUOTIENT 3 : represents 3-bit of the REMAINDER for example: decimal vector 9.125 is represented in binary as A_UNS="1001.001" the simulator will show A_UNS as 73...
  5. K

    how to IP block that no one can modify/see its contents???

    ncprotect I have several HW implementaion blocks that I develop. I want to share them but I don't want the other ppl to see its content. Just to use it as black box. something like EDIF files. how I can generate like this desire???
  6. K

    Case-statement in synchronous process.

    synchronous process with non blocking when I have a case statment in a synchronous process, can I leave WHEN OTHERS with no value??? In Aynchronous process I should insert values to make sure that no latch will be produced. but what about synchronous process???
  7. K

    Implementing tri-state buffer at the bottom hierarchal block

    What is the functionality different or the implication of next two situations: 1. An output of OR'gate that is feeding TRI_STATE buffer and that buffer is feeding a PIN output. 2. OR'gate output is connected directly to a PIN output while OR'inputs are connected to two independent TRI_STATE...
  8. K

    How to implement MOD function in Hardware.

    implement mod Given two inputs A[7..0] and B[7..0]. Design a Hardware block that its inputs are A, B and output C while: C = A MOD B.
  9. K

    What are the implications of using Integer instead STD_LOG

    in Counter RTL; it is preferable to use INTEGER'type instead of STD_LOGIC_VECTOR. why???
  10. K

    When giving Set-Up or Hold time parameters; does the min/max

    In typical Data-Sheet, it is given MIN/MAX values of several parameters such as Set-Up and Hold time. The question is: Does that MIN/MAX values are result of different length of traces that are routed between the DIE and the PADCELL??? or what???
  11. K

    Is there any reason that designs adopt Clock Positive Edge??

    Generally each design that I meet consider the the clock at its positive edge only. While it is not considering it at Negative edge except special cases. My question is Why Positive Edge and not Negative Edge???
  12. K

    Interview in a fab-less company - NAND Flash

    a fab-less company I have an interview in a fab-less company that provides solutions for the non-volatile memory- NAND Flashe. The position is Logic Designer Engineer. I have more than 6 years Experience as FPGA/ASIC Engineer. I wondered what they can ask me in the interviews. The company...
  13. K

    Does NC-Verilog work on Windows platform?

    1. Does NC-Verilog working under WindowsXP/Windows2000 paltform??? 2. What is the latest-current version of NC-Verilog???
  14. K

    Doubt about racing at JK-FF

    Supposed we have a JK-FF that its J'input tied to START signal and its K'input and its RESET tied to STOP. START and STOP are synchronized to CLK. When rising CLOCK and START goes HIGH then the FF'output goes HIGH. What will happen if later START goes HIGH??? is there any problem with this...
  15. K

    How the synthesier consider CONSTANT and SIGNAL

    Supposed we shall add a constant to STD_LOGIC_VECTOR: A_UNS : in std_logic_vector(3 downto 0); Y1_UNS : out std_logic_vector(3 downto 0); Y2_UNS : out std_logic_vector(3 downto 0); . . signal y_uns_std : std_logic_vector(3 downto 0); constant y_const : std_logic_vector(3 downto 0) :=...
  16. K

    The negative edge triggered FFs

    The refernce of Setup/Hold Time in FFs with POSEDGE is the rising edge of its CLOCK. But!!! When we have FFs with NEGATIVE edge, what is the clock reference??? is it the rising edge or the negative edge???
  17. K

    How do you generate GRAY counter???

    To generate GRAY by binary counter that its outputs routed through XORs array then we conveted the BIN to Gray. Or To being with a counter that is designed to generate Gray sequence WITHOUT using XORs array??? What is the considerations???
  18. K

    If setup time is met, so how hold time violation maybe occur

    supposed cascaded two FFs, FF1 and FF2, thought combinational logic. while D1 <= X; X is the input of FF1. D2 <= Q1 but throught comb logic. Y <= Q2; Y is the output of FF2. ----------------------- Relevant parameters for FF1: Tcycle. Ts1, Th1, Tc2q1 For FF2: Tcycle, Ts2, Th2, Tc2q2...
  19. K

    How Gray counter promote overpowering GLITCH???

    I already read an article regards Aync FIFO: https://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf As I know in order to overpower GLITCH while COMPARING two binary counters outputs, we may sampling the output compare by a FF. Then we will not have any GLITCHs. The article...
  20. K

    Is is necessary to include a counter under MOD???

    Once, I noticed that counter of 4 bit implemented in VHDL while . . signal counter : integer range 0 to 15; . . elsif clk'event and clk = '1' then . counter <= (counter + 1) MOD 16 . . is it necessary??? Does this MOD promote the synthesizer effort???

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