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  1. W

    What method to use for translating the address in a memory?

    Re: memory manage. Thanks! My question is what method can improve the translation performance for the large address space. The basic principle is multi-level page table, so, the efficiency will be poor. We'd better improve it. Regards, Wolfkin
  2. W

    What method to use for translating the address in a memory?

    memory manage. Hi, Dear all, I issue a challenging topic that is about memory manage. It is known, the memory manage has 2 primary method--paging and segment. Their primary elements are very clear. In general, the paging is popular. In the new situation, some new architecture have very large...
  3. W

    what may i do after synthesis?

    by aegean's nickname! the name separate by a dot, and the posfix part is chou that is zhou in chinese, but, in general, chou don't rgard a name in english. so, i think aegean is a chinese. ok? best regards! wolfkin
  4. W

    what may i do after synthesis?

    thanks very much! i'll do those! to, aegean.chou, are you a chinese? i am! thansks & best regards! wolfkin
  5. W

    what may i do after synthesis?

    hi, chip123, thank you very much! this design is a interface of a adc. that adc is inverse, so, for avoiding ip entanglemant, it must modify some parts such as interface. i have synthesised the design and simulate it by hspice, i don't know what other works must do. for i do front-end work ago...
  6. W

    what may i do after synthesis?

    hi, dear all, i have synthesis the my design. but, i don't know what i may do in future, please someone tell me! thanks!
  7. W

    REDHAT 9.0 work with EDA tools

    hi, dear all, this is how to install dc in rh8.0 or least. before install, you must modify the scripts! in editor, find "status", some section will judege it, then some variables, one, set iso and another set toupper & taz. you must mask these sections by commenting. now you may execute the...
  8. W

    help me! how to generate an edif file in synplify asic?

    hi, deal all, how can i generate an edif file in synplify asic?
  9. W

    How to configure my EDA tool licenses under Linux O/S ??

    Q1... A1: you haven't set this hostname! you can execute ifconfig command to set it or by gui. this is a good way, in /etc/sysconfig/network, chang the HOSTNAME's value that localhost.localdomain to your-hostname.localdomain. Q2... A2: don't modify the that file that in your home directory...
  10. W

    Help me design a 32 bit ALU in VHDL

    if you can read chinese document,you may read the following document: https://61.129.72.81/advance/skill/ALU_design.pdf https://www.51ic.net/icdesign/mcu.pdf https://gzmcu.myrice.com/download/files/tutorial_books/other/ALU_design.pdf
  11. W

    How can i install cadence ldv v3.40 in redhat linux7.2?

    I have download the ldv (ncv-complete-03.40.s016-lnx86.tar.gz & ncv-complete-3.40.s009-lnx86.tar.gz), but I don't know how to install it.
  12. W

    Help me about cadence ldv v3.0!

    Oh! thanks, I'll try it Thanks for your help!
  13. W

    Help me about cadence ldv v3.0!

    Hi sbob, Thank you very much! I'm a IC logic design engineer, and have 2 years experience. I once designed a 16-bit dsp and a 32-bit cpu. I work in front-end, the design tools include modelsim, fpga complier etc. Ihaven't applied the verilog-xl or ncverilog. I want learn it and...
  14. W

    Help me about cadence ldv v3.0!

    the probleme as of old. Dear sbob: Thank you for your timely help! I apply the license, but appear the same problem. Can you tell me how I set the license, the platform is windows 2000.
  15. W

    Help me about cadence ldv v3.0!

    Thank you very much! to sbot: I'll apply it at once
  16. W

    Help me about cadence ldv v3.0!

    ncverilog $recordvars $dumpon When I run it , I can't add any signals to waveform window. Operate following: a:1. Run the "Affirma launch tool". 2. Select the "Verilog","Verilog-Xl Desktop","Graphical" to creat a session. 3. Add a verilog file "Test.v" and...

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