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I am doing PCIe physical layer verification. For Gen1 and Gen2, PCIe transmits 20 bit data and receives 16 bit data. I am in the process of bulding up a test bench environment for this.
I am actually preparing an expected data buffer. This is 16 bit buffer. Need to take 16 bits...
I am working on verification part of UTMI transceiver. RTL for digital part inside UTMI+L3 is developed and I am supposed to develop TB setup from the scratch. Please suggest a TB architecture for the same. Also, let me know what type of assertions are better to use in this scenario.
From a clock generator module, how to generate clocks of different frequencies?
For example, my design has different clock domains at 25MHz,66MHz and 125 MHz.
From the same clock gen, how to generate all these clocks?
Simply, how to increase or decrease clock frequencies?