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  1. K

    write_spice_deck in primetime: extracted netlist format

    I got it solved. The issue was that VSS, VDD, bulk! should be declared as global and be removed from .subckt ie: *.GLOBAL bulk! *.PIN bulk!
  2. K

    write_spice_deck in primetime: extracted netlist format

    hi all, I am using the command write_spice_deck of primetime because I want to simulate a path of my design in spice: write_spice_deck -output <spice_file> -sub_circuit_file <extracted_netlist> $timing_path however, primetime complaints for the format of my extracted netlist: Warning: SPICE...
  3. K

    dc Vs primetime: reasonable slack or not?

    hi again, Are the info I provided incomplete? I am just looking for a "yes, its reasonable" or "no, it seems that you did something wrong". Can someone that has done something similar before just express his opinion? thanks! -Kostas
  4. K

    dc Vs primetime: reasonable slack or not?

    hi all, I get a significantly different slack in dc and primetime. Since I am a newbie, I am not sure if this is reasonable or I did something wrong. the details: I synthesized my design in dc and I fed the synthesized netlist to primetime (with exactly the same constraints file and the same...
  5. K

    How can I get a flatten netlist?

    hi all, i m a newbie and i have the same problem (flattening my netlist). Here's the exact problem: I synthesized my verilog design using RC and I wanna feed the synthesized netlist to Primetime. For some reason "read_verilog synthesized.v" cannot read a hierarchical netlist, since all...

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