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I have an onboard UCD9240 which need to be configured, but it has just one PMBUS interface, and I searched the web, but cannot find a cable supporting PMBUS or I2C. Pls someone tell me where I can find this kind of stuff, thanks a lot!
thanks for your reply! I have solved my problem, by moving the layer in my PCB file.
But you mentioned "keep your drill and gerber fabrication settings same" , will the position of drills in gerber files be different from these in PCB files, if some settings are not correct?
Hi, I was drawing the PCB files in Altium and found something weird.
The coordinates of layers seem to be different, as show in the picture. The drill guide layer is not right below the other layer, but a little misplaced.
Is there some way to adjust this layer to the right position? thanks a lot!
I'm plotting a PCB file based on a reference design (so no schematic files) and encounter a problem.
One chip with FBGA pinout gets the pad inside out through via. Now I want to connect this pad to another place, but just cannot select the via connecting to it and change its net.
Thanks a lot.
But would you please explain it in detail? I assumed that the precompiled modules you mean is the DB folder under project folder, containing .tdf files etc. Say another user has many modules, and your design is one of them, so how to make use of the precompiled modules and...
I mean that Packaging my HDL code into some kind of file format(IP) that can be recognized by FPGA tools, so that another person can reuse the IP I creat, but don't know the exact algorithm or implementation in it, like a blackbox, only function and ports can be seen from outside. Just like the...
hi, recently I'm doing some PCB work with virtex-6 FPGA (FFG1156), but cannot find the symbol while drawing schematics. The Altium version is 6, is it too old for that?
Besides, the virtex-5 symbol in Altium is composed with IO banks, why not in its original form - the square box?
Any help is...
Glue logic here to form 64*64 multiplier is just a few addings of Partial Products, will that degrade the performance so much?
Besides pipelining will increase clock cycles to two or more, that will limit the throughput.
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I implemented a 64-bit multiplier using Altera Quartus MegaWizard Plug-In Manager. The device is cyclone III series. But the classical timing analysis shows that it cannot even meet when tpd=20ns. I wonder why it can be so slow when the device is made with 65nm process, is there...
I'm using Quartus 9.0 signaltap for simulation on Altera FPGA. Now I can watch the real-time wave of output PIN in my design, but the wave soon disappeared. So I wonder if signaltap can automatically record the wave for later use.
Thanks in advance~~
My project need to generate a low frequency clock for ASIC use from external high frequency clock input. So there must be a frequency division.
As far as I know, it can be implemented with counter(the clock skew and driver capacity are OK?) and PLL, but don't know which one is more...
well, I just intergrate the similar conbination logic into one logic and reduce the Combinational area, so the Net Interconnect area decrease. I don't know if I say it clearly. For instance,I implement logic in different 'case', now all of them can be intergrated into one.