Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. Z

    How To Run Calibre LVS/DRC

    That's easy. you need a calibre run deckfile (which you can get from foundary) and use "calibre -gui"
  2. Z

    Smartmodel question regarding design using xinlinx isev4

    Smartmodel question Does anyone have experience in simulate using smartmodel and design using xinlinx isev4. I want to construct a board level simulator enviroment using these two tools. I need using smartmodel's 386 model and fpga designed using xinlinx. How can i do this?
  3. Z

    Anyone with experience in designing 64bit CPU?

    Thanks above everyone. Yes we have much people doing this project.And i am charging EDA for this project. So i am much interested in such asic design flow. Say truely i am not worried about the IA64 architecture complexity.We have great man for design this. The compiler question is too. Now i...
  4. Z

    Anyone with experience in designing 64bit CPU?

    Now i am just wondering for designing macro .Does there any commercial tool for design . BTW we are not clone IA64.
  5. Z

    Anyone with experience in designing 64bit CPU?

    Thanks asic. I will be glad to think through sun's cpu . BTW anyone can point some best tool to design cpu ? If i buy i will share with everybody here.
  6. Z

    Anyone with experience in designing 64bit CPU?

    I am not joker. I am seriously. If someone is interested in helping me pls pm me. Now we have experience for developing chinset about 4 million gates and want to do more. Now i am new for design cpu and want to know the difference between chipset and cpu. I want to know the basic for design...
  7. Z

    Anyone with experience in designing 64bit CPU?

    First thanks for gabby. Now i am involving in designing a real more complex cpu than embedded cpu. This is designed compatible for intel IA64.So now i want to make friends with those who have made work for intel or ibm.I need to know how they design such cpu .
  8. Z

    Anyone with experience in designing 64bit CPU?

    design cpu Now i have a preject to design a 64 bit cpu . I have some question to ask whom have experience in doing that.pls pm me if you have experience with that and glad to help others.
  9. Z

    why pt2002.3_linux gui does not work ?

    can marsgod be so niced to share us your synopsys product? We will apprecicate you very much
  10. Z

    Poll: ASIC design tools for Solaris

    Tool for asic Here is my list for my last finished work : synopsys dc,primttime,formality,vcs(like it), transeda cover asic vendor's floorplan tool and p&r tool and gate sim tool.
  11. Z

    Spy program in EDA tools?

    The best way to avoid is to seperate two sub network and unplug the netwrok cable.
  12. Z

    how to use ip core and design core?

    I have two question : 1.Have anybody experience in designing asic using ip core . And what kind of core do yur use.? 2.I want to summerize our previous design work .And i want to make some ip core for next usage.For example fifo and control unit. Which tool do i need? Any comment will be...
  13. Z

    tetramax 2001.08 for linux

    Can any one list the actual long path name in the synopsys f*p site.If somebody with normal account can list everyone will be appreciated.
  14. Z

    best tool suite for next generation VLSI

    Yes. We also will let company sales manager to introduce their products.But they are salers not engineers.And i think this place will be more open and accurate by yours friend.
  15. Z

    best tool suite for next generation VLSI

    Much thanks for kunjalan.For some reason I am sorry I can't tell more clearly for my project. I can only say this is about 0.1um level design . But if someone have experirence in design for 0.1um pls let me know. I now just have two question : 1.delay model in 0.1um.Is the model much different...
  16. Z

    best tool suite for next generation VLSI

    hello every one. Now i working for designing next generation VLSI project in china.Can any one tell me the best tool suite for such thing. Now we use synopsys dc for front design. We are going to do about ic place & route .Any suggestion will be apreciated. We want the best tool, for...

Part and Inventory Search

Top