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  1. G

    mismatch analysis using Monte Carlo

    I'm little curious regarding what you are trying to convey. In the mc modelfile I have statistics block having both process and mismatch sub blocks and I include the original model file for the nmos and pmos in that mc model file. So, please clarify regarding what cellname you are suggesting to...
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    mismatch analysis using Monte Carlo

    monte carlo process mismatch Hi, When I attach my mc model file, on montecarlo simulation I was observing the mcdata and mcparam file generated. I did so to observe whether the variables I'm mentioning in my model file varies. While doing the process variations I found the parameters varying...
  3. G

    measuring offset voltage using montecarlo

    Then what is the advantage of going to Montecarlo mismatch analysis?? I thought ,depending on the correlation between the transistors the simulator would change the parameters statistically and so forth.. Is my belief arguable??
  4. G

    measuring offset voltage using montecarlo

    I don't understand what do you mean by the difference in the models. Say I'm testing for a diff pair, I'm going to attach the same model lib to both the transistors. Where do you ask me to bring the difference. Please clarify. Thanks, Gayathri
  5. G

    measuring offset voltage using montecarlo

    Hi, I'm trying to do the mismatch analysis using montecarlo simulations for a simple diff pair..I selected "mismatch only" option and tried plotting the drain current for the diff pair transistors. I expected a change in the two currents so that I can divide the difference by corresponding gm...
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    Whats the sampling accuracy requirement?

    Re: Sampling accuracy Hi, Do you need to look at the Aperture jitter and delay occuring during sampling?? Even I need clarifications on how the jitter time specification comes into the design parameter. It's because, I could find the importance of jitter time limit in the ENOB (Effective...
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    How to simulate eye diagram in HSpice?

    Re: Eye diagram Hi, In the calculator option of most of the tools I've found Eyediagram plotting option on which it will be plotted..I've found them in Cadence Virtuoso Analog Design environment and Mentor Graphics - System vision. GD
  8. G

    [help] ac-coupliing capacitor can be used mos capacitor?

    Re: [help] ac-coupliing capacitor can be used mos capacitor Hi, Actually what is mim capacitor, can you plz expand /explain it..With the Mos capacitors if we see, though area wise we get the adv..I think in stability ( like leaking and other issues) arer not good with it.. Regards, GD
  9. G

    About simulation of hot-electron degradation

    Hi, Did you check the properties of your transistor object in the simulation tool.In cadence ICFB I've found "Hot electron effect" as an option which on enabling the tool will take care of the rest of calculation... Regards, GD
  10. G

    Question on Settling Time, Slew Rate & Rise/Fall Time

    settling time op amp Regarding the importance of Settling time.. I think it is important than the rise/fall time. Because only when an output signal from opamp settles to a point (after undershoot or overshoot) it becomes usable to the next stage..So, Settling time also gets into account while...
  11. G

    A planar Transistor??

    electronrancher, Thanks..I have one more query.That is ..while talking about Optical interconnects in place of electrical interconnects, Optical interconnects claim an advantage of Planar Signal Crossing..Can you throw some more light on to it.. GD
  12. G

    A planar Transistor??

    Recently INTEL has announced a 45nm SRAM, there I found that the Transistors being used are still Planar? Is it related to Fabrication technique? Can somebody throw some light on it. GD
  13. G

    Frequency synthesizer - Frequency Multiplier- Difference?

    Both Frequency synthesizer - Frequency Multiplier can be incorporated using PLL.What is the difference between the two both functionally and in construction part of it. GD
  14. G

    LPF in PLL -- Reasons explored??

    MSGHP, Thats right. I accept. But I have one more question. According to this concept of using LPF to cut the component f1+f2, how can we justify the use of PLL as frequency multiplier. That is...Let us assume that locking to f1 is done. Now at the feedback we divide it by 2( to have 2*f1 at...
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    Can a voltage divider act like a voltage amplifier?

    v_c, I accept your idea.But I have one more doubt. In the case of micro wave solid state devices we talk about negative resistance with no relation to the power generation. That is when the voltage increases the current across decreases.. some thing related to the phase shift of 180 which gives...
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    What do the terms fan-out and fan-in mean?

    calculating buffer fan out from drive strength IanP, I have a doubt.As per the example given,you said sourcing current .5 is the max. OK I accept it.Because if the device loaded than .5 each component will get less current so that they might not turn ON. But why the sinking current has to be...
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    LPF in PLL -- Reasons explored??

    Actually if we use a phase detector in the PLL, then we use LPF only to cut the transients that comes out from the detector along with a DC voltage that denotes the phase error.Because only when the control voltage to the VCO is stable, it can work properly. If we make use of a Frequency...
  18. G

    Can a voltage divider act like a voltage amplifier?

    Sorry v_c, I donot get your point. Why do we need an additional supply.Can you throw some more light into it. GD
  19. G

    Optical clock generation but electrical distribution??

    Actually in microprocessors especially, to operate it in G Hz we surely require a optical intervention because of the frequency instability invoved in crystal oscillator or any other at high frequency.In such a case why donot we look for global clock distribution using optical pulses.Optical...
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    suggestions for a good part to do RF

    Can Optics help here? That is can a optical signal be transmitted for the info to be passed on.

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