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  1. U

    Low resistance between chip supply pins

    Hi all, My ADC chip has very low resistance between its supply pins (VDD and GND) for the digital part (ananlog part is fine its in Mohms range). It is almost 600ohms with VDD of 1.5V. So digital part which should not draw any static current must be consuming about 3mA of current without any...
  2. U

    How to increase vds if I bias a transistor in linear range?

    Re: One basic question Vds is usually set by upper transistor
  3. U

    Calibre extracted simulating as schematics

    thanks buddy, I found the mistake I was making which was very stupid of me then. When one changes the config view, he must run the testbench using config view (not with the schematic view). Rest worked great. However, I did not use your spectre method which seems a bit complicated to me...
  4. U

    Low SFDR of SHA at nyquist input

    @iamxo Hi, did you figure out the solution? Can you please share your thoughts about this.
  5. U

    Calibre LVS and extraction

    Hi erikl, In your pdf, you mentioned "Now, within ADE add the netlist to the model setup". I dont understand this point. Can you please elaborate on this point. Also, do you have experience using calibreview. I got the extracted view from the layout in calibre format. But the calibre view gave...
  6. U

    Calibre extracted simulating as schematics

    Hi all, I did extraction from calibre xRC and got "calibre" view. When i simulate it by changing the config view of the testbench I get the same simulation results as that of schematics. Where I am making the mistake? I did extraction with Assura and its av_extracted shows the desired behaviour...
  7. U

    opamp of Pipeline ADC latter stages

    Increase the opamp gain and let it settle completely. It should solve your linearity issue.
  8. U

    opamp of Pipeline ADC latter stages

    Its here https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5338964&isnumber=5338937 However its a conference paper, so many details not given. /Noman Hai
  9. U

    The importance of loop gain

    Yes you can still use loopgain simulation methodology in cadence. However before running "stb" analysis you have to run transients till your CM is settled. An easier way is to use ideal CMFB circuit and then do can skip the transient analysis part. My answer assumes you already have good...
  10. U

    How to simulate fully differential ota with sc cmfb

    you can run trasient analysis until your CMFB is settled. Now run AC analysis and in its option menu click yes "prevoppt". It should do the trick for you.
  11. U

    Can I convert 2 8bit adc to a 12 bit adc?

    I don't know if you all are satisfied with this answer?
  12. U

    Can I convert 2 8bit adc to a 12 bit adc?

    I beg to differ here. You can use 2 8-bits ADC to get 12 bits but it won't be a 12-bit 'ADC'. Basically to get 12 bits you need sampling capacitors of about 2^4 times higher than used in a typical 8-bit implementation to satisfy thermal noise requirements. Also, opamp must have 2^4 higher gain...
  13. U

    LOCKING PROBLEM IN CADENCE

    Here what I used to do. 1) Type clsAdminTool at shell prompt, and you will get a > prompt 2) Type are /<you_path>/folder_name (folder name is from the directory you running the cadence). This will erase the locks. In order to check which files have edit locks, simply type ale...
  14. U

    opamp of Pipeline ADC latter stages

    iamxo, I think you are missing very important point here. ft of an opamp can be given as ft=β gm/Cl. When you scale the stages, the load feedback factor remain constant however, the load capacitance is reduced half (assuming you scaling down by 2 approx and not taking into account unscaled...
  15. U

    Assura RCX / QRC Questions

    assura rcx no technology directory found Yes I second oermens comments as I also had the same problem and the setup suggested by oermens is the only way.
  16. U

    can anyone suggest websites for layout

    https://rficdesign.com/VLSI/analog-layout
  17. U

    multi-device Assura LVS error

    malformed devices assura lvs Yes, I tried it and <x:y> method works. I will look into the rules file to find what you mentioned. Thanks anyway.
  18. U

    multi-device Assura LVS error

    parallelmos Hi guys, When I run LVS on a circuit containing FETs with multiple deices then I usually get LVS error for that device. Error being malformed devices. I said usually because for some devices it does not show this error. So I get the way around is to put exclusive m number of devices...
  19. U

    ft of mosfet nmos pmos 0.18u technology

    cgg spectre bro! you might missed that aF is 10^-18 So you will get 49GHz, not MHz.
  20. U

    ft of mosfet nmos pmos 0.18u technology

    nmos-pmos First connect DC source "Vgs" to an NMOS transistor. Another DC source for Vds and ground to source and connect bulk to source. Now sweep DC Vgs using DC sweep. In order to plot "gmoverid" you need this file. Please find herewith the stimulus file (It can have any name,. In this case...

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