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  1. J

    Hold time pass on FF, but failed on TT?

    Is it possible to pass the hold time check on Best Corner, but failed on Typical corner? Any one can help me out? Thank in advanced Jax
  2. J

    Any method to make schematic transfer to verilog netlist??

    Under cds 5.033. I need a synthesizable verilog netlist in APR flow? Any advise? cheers jaxshai
  3. J

    help: how to make a routable P&R with SE?

    Hi Folks, i am a rookie for using SE. There is a problem I could NOT solve for few weeks. I could NOT make my design finish routing . I have reduce the ROW Utilization , increase the distance between IO and Core. But it still doesn't work. That made me very depressed. Is there any good advice...
  4. J

    Anybody has idea about the job of IC integration Eng.??

    :) What 's the major responsiblity of this job?
  5. J

    Any diode whose Reverse Breakdown voltage is below 4.5V ??

    Any diode whose Reverse Breakdown voltage is below 4.5V ??
  6. J

    Problem of using ATI 9550 in RedHat 7.2

    I want to install IC 5.0 in RedHat 7.2,but X windows Could NOT run ,due to RH7.2 doesn't support my ATI 9550 vedio card. Is anybody could give me some help? Should I download newest driver for my vedio card?

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