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I have 8 numbers like -398.1234 , -14.1898 etc and I have 8 signals generated in the design .
I need to compute
y = c1* x1 + c2 * x2 .... + c8 *x8 ,
where c1 , c2 etc are the constants and x1 , x2 are the signals to the block .
What is the best way to code this ?
since these are...
I am using dc with standard LL 130nm library to synthesize a vhdl logic .
I removed the
and instead of std logic used bit and bit_vector in intialization
while analyzing in DC
in DC ,i am try to get STA for the path b/w two flip flops which are clocked at clk and clkby 2 respectiveley . in report_timing ,It is showing no delay corresponding to the combinational logic cells in between these flip flops
I even tried various version on DC but wasnt able to get hold of...
I made a design which has 5 divided(internal) clks(clkby2,clkby4 etc) derived from main clk by a counter.
i am synthesizing it via DC specified the divided clocks by create generate clk and main clock by create clk commands and there respective constraints wrt to main clk & divided...
i synthesized my code (verilog) containing mainly additions and subtractions and am doing post synthesis simulation in modelsim
in modelsim wave i see,
instead to obtaining differences of two registers , i am now obtaining difference divide by 2
I am not able to figure out the problem.
Hello all ,
i am doing post synthesis simulation in modelsim.
I synthesized via DC with 130nm faraday library ... timing reports in DC showed no voilations of setup and hold and a slack of 228 ns for 1 Mhz .....
But in modelsim it is giving large number of setup voilations
i am confused...
I am trying to synthesize gate level logic of my behavior level code(verilog) by design compiler . i am using faraday 130nm library. I have a divided clock derived from a 7 bit counter . I made the network as dont touch (counter) so that synthesizer wont try to optimize and modify it...