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  1. DZC

    Choosing specification and designing flash type ADC

    flash adc design flash seems not a hot topic now except that you've got some brilliant idea already. Good luck !
  2. DZC

    How to write the TT case for 0.35um TSMC 2P4M process parameter model?

    technology file Do you want to write a parameters all by yourself? I advice you to search the internet to get a ready-made one.
  3. DZC

    Why high gain in opamp ?

    You'd better learn something about feedback theory to full understand it!
  4. DZC

    use instrumentation amplifier as op amp

    I think so.
  5. DZC

    How about this kind of negative feedback

    You'd better draw the schemetic for others to help U.
  6. DZC

    i should select a DAC which have 12bit ,5v,speed 1M-5M

    **broken link removed** Added after 3 minutes: It's the "Amplifier and Data Converter Selection Guide" from TI.
  7. DZC

    :?:How to clock such high performance ADCs?

    But is it noise to embeded the PLL in to a ADC?
  8. DZC

    current mode and voltage mode ckt

    Generally spesking,Current Mode circuit are useful in high speed circuit design,say CML(current mode logic). However,at the expense of power consumption... I recommend you some book in this subject as follows: 1.Model and Design of Bipolar and MOS Current-Mode Logic 2.CMOS Current-Mode Circuits...
  9. DZC

    Low/high dual Vt Library

    High Vt guarantees low leakage current(thus low power consumption) and robust logic while low Vt is usually benefit for analog circuit in view of voltage swing (thus dynamic range). Added after 4 minutes: Dual Vt combine both advantage of them,thus suit for mixed signal design. Besides some...
  10. DZC

    How to add a dc voltage to a Differentiator in verilog-a?

    add dc voltage Did you define "outcom" for the wrong property
  11. DZC

    :?:How to clock such high performance ADCs?

    I found ADI have release the AD9461(16-bit,130Msps),also TI ADS5474(14-bit,400Msps). In sampling theory the clock rms jitter should be less than 50fs? Is there any equipment that can offer such low jitter clock? How do we generally clocking such high performance ADCs?
  12. DZC

    Any one help in designing a pipelined ADC

    I suggest you read some phd papers to start learn about it. Check: https://kabuki.eecs.berkeley.edu/adc/adc.html
  13. DZC

    Need info about designing two stage amplifiers

    Re: two stage amplifier It is totally different approach to design a amplifier and a comparator. The key point is, in my opinion, comparators are open loop circuit and there's no need for compensation, which is really important in amplifier design...
  14. DZC

    Need some interview questions.....

    I found it a really wonderful page...
  15. DZC

    how to design a fully differential opamp with sc-cmfb

    Check in this forum for the EE240 projects from Berkeley and I'm sure it will help you a lot.
  16. DZC

    How to get Kn' and Kp' from a given PDK?

    I've tried two ways: 1.K'=u*Cox; 2.using a current drived dioded connected transistor and calculate from a output data; but I found the result vary as much as 100 times??? I'm afraid there's sth wrong with my method. How do you usually get the K'?
  17. DZC

    Analog Delay locked loop circuit THESIS

    design of cmos analogdelay circuit The following material may be helpful for you.Actually I've benefited a lot. Regards.
  18. DZC

    What is the most commonly used rail-to-rail OP structure??

    https://www.designinganalogchips.com/_count/designinganalogchips.pdf
  19. DZC

    What are the rules for biasing an OP??

    How to bias a OP?? The general goal is to bias the transistors which signal travels in the saturation region to work with large gain and good linearity.Better to save more swing at the same time.
  20. DZC

    What is the most commonly used rail-to-rail OP structure??

    Re: What is the most commonly used rail-to-rail OP structure Also Willy Sansen's slices provide more examples.

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