Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. amit.dounde

    algorithm to find the level of an element in a design.

    level of a design anybody has an algorithm to find the level of an element in a design. thanks Amit
  2. amit.dounde

    timing analysis - request for resources

    Re: timing analysis downloaded....will take a look.. thanku
  3. amit.dounde

    timing analysis - request for resources

    timing analysis hi any one knows a good book where i can learn how to do timing analysis. i have rabaey text..but i feel it is not sufficient. any book concentrating more on timing analysis would be helpful. thanks
  4. amit.dounde

    floting point unit -functions to be supported

    floting point unit Hi I am trying to design a 32 bit FPU. I just want to know the number of functions that a FPU should support and also the functions.
  5. amit.dounde

    pll for ddr3 apps- how to decide the reference frequency?

    question on pll i am implementing a pll for ddr3 apps. the vco freq range is 100-800Mhz. how do i decide the reference frequency?
  6. amit.dounde

    need to select topic for PG degree - LVDS, PLL or ADC?

    Re: help me pls if i choose LVDS for my project what could be the min. data rate that i need to choose. thanks
  7. amit.dounde

    need to select topic for PG degree - LVDS, PLL or ADC?

    Re: help me pls appreciate your replies. I was also thinking of TS ADC. but i am not able to find any good material and papers. one more thing, has anyone done TS ADC in cadence .18um. Any information in this would be helpful
  8. amit.dounde

    information needed on standard books on LVDS

    information needed anyone knows any standard book on LVDS.
  9. amit.dounde

    need to select topic for PG degree - LVDS, PLL or ADC?

    help me pls i need to select a topic for my PG degree. we have to give the topics by next week. i have shortlisted a few. 1. on LVDS(low voltage differential signalling) 2. PLL 3. time stretch ADC i am not sure whether these projects can be completed in one year. also not sure of which ieee...
  10. amit.dounde

    cadence and the tme-stretch analog-to-digital converter

    Re: question regarding ADC The information in wikipedia says that the time stretch processor is generally optical. I am not quite sure how the streching is done. It uses a dispersion compensation fiber etc etc. didnot understand to be frank. but the result is to produce a chriped pulse. i...
  11. amit.dounde

    cadence and the tme-stretch analog-to-digital converter

    question regarding ADC can a Time-stretch analog-to-digital converter(https://en.wikipedia.org/wiki/Time_stretch_analog-to-digital_converter) be simulted in cadence.
  12. amit.dounde

    need good source for LVDS material and project

    Re: information needed thankyou. any thesis works??
  13. amit.dounde

    need good source for LVDS material and project

    information needed anyone knows any good source for LVDS material and project
  14. amit.dounde

    where to get PLL info

    very helpful
  15. amit.dounde

    suggestions concerning good one year project on switch caps

    Re: help needed thanks.references to any papers would be helpful. i was also thinking abt plls for a 1 year project. any suggestions:?:
  16. amit.dounde

    suggestions concerning good one year project on switch caps

    help needed can anyone suggest a good one year project on switch caps
  17. amit.dounde

    ieee paper request- Low power CMOS fully differential...

    ieee paper request Low power CMOS fully differential variable-gain amplifier Spiridon, S.; Opapos;t Eynde, F. Semiconductor Conference, 2005. CAS 2005 Proceedings. 2005 International Volume 2, Issue , 5-5 Oct. 2005 Page(s):383 - 386 vol. 2 Digital Object Identifier 10.1109/SMICND.2005.1558806
  18. amit.dounde

    Cadence question concerning virtuoso design environment

    Re: Another cadence question plot square root of id VS Vgs(or vgs-vt) and find the slope... then use the drain current equation.
  19. amit.dounde

    paper request - A CMOS fully integrated 1 GHz and 2 GHz ...

    another paper request A CMOS fully integrated 1 GHz and 2 GHz dual band VCO with a voltage controlled inductor Tiebout, M. Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European Volume , Issue , 24-26 Sept. 2002 Page(s): 799 - 802 Digital Object Identifier

Part and Inventory Search

Top