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  1. U

    Low resistance between chip supply pins

    Hi all, My ADC chip has very low resistance between its supply pins (VDD and GND) for the digital part (ananlog part is fine its in Mohms range). It is almost 600ohms with VDD of 1.5V. So digital part which should not draw any static current must be consuming about 3mA of current without any...
  2. U

    Calibre extracted simulating as schematics

    Hi all, I did extraction from calibre xRC and got "calibre" view. When i simulate it by changing the config view of the testbench I get the same simulation results as that of schematics. Where I am making the mistake? I did extraction with Assura and its av_extracted shows the desired behaviour...
  3. U

    multi-device Assura LVS error

    parallelmos Hi guys, When I run LVS on a circuit containing FETs with multiple deices then I usually get LVS error for that device. Error being malformed devices. I said usually because for some devices it does not show this error. So I get the way around is to put exclusive m number of devices...
  4. U

    question about CMFB- using opamp without using the CMFB

    cmfb basic Hi all, I have a question about SC CMFB. Is it possible that after the CMFB settles to its desired voltages, one can use the opamp without using the CMFB. Like the case in an algorithmic ADC, where opamp is used in few clock continuously without the CMFB being used.
  5. U

    conservative option simulating bootstrap switch

    hi all, I am simulating a bootstrap switch using conservative option in spectre. However I an getting convergance difficulties. When I go to moderate option, the simulation works fine. I have read Ken Kundert's book and i tried to fix these convergence errors but could not fix these. Has anyone...
  6. U

    opamp output common mode varying with input CM?

    Hi fellows, I designed an gain boosted telescopic opamp with ideal CMFB. Now problem is when my input CM changes even around ±100mV output CM changes a lot (900mV to 600mV). And it is also not fixed for any range of input CM, which seems to be weird. I am attaching the schematic of my opamp. I...
  7. U

    PM and GM of stability analysis

    Hi, I designed a simple cascode opamp and did the stability (stb) analysis. Mag and Phase plot is perfect. However when I get the stability analysis summary I am getting negative values for Phase margin and Gain Margin. The phase when my loop gain crosses 0dB is -93 degrees. However, in...
  8. U

    virtual ground of a diff opamp having different ip op CMR

    virtual ground in op amp Hi, Suppose I design an fully differential op-amp having different input and output common mode (say ICM=0.75V and OCM=1V) and I will use this op-amp in a SC circuit. During the amplification phase, due to high gain of the op-amp, the input nodes of the op-amp are at...
  9. U

    Open-loop OTA simulation and PM @ ft or the closed-loop frequency

    OTA feedback Hi all, For example I have op-amp specs for a 100MHz 10b pipelined ADC. I found out that ft=600MHz. However my feedback factor β=0.33 (say). During the open-loop ac simulation, do I have to look at the PM @ ft (600MHz) or the closed-loop frequency (ft * β = 200Mhz). This op-amp...
  10. U

    How to check the stability of the CMFB loop?

    I have some confusion regarding the real SC-CMFB circuit. When i use ideal CMFB everything seems good. But when I use SC-CMFB then I look at PSS and PAC analysis to find the gain and phase margin, they do not come good. Now after PSS/PAC analysis, I can not see DC operating point ( in fact one...
  11. U

    connecting diff i/p o/p common mode opamps together

    Is it possible to have different input and output common mode of an opamp? Which I know is possible, then how to connect the same opmps in pipelined fashion? Do we have to do some level shiting? and how? As i am thinking to design a gain boosted telescopic opamp but then there input and output...
  12. U

    Finding bandwidth using PAC

    Hi, I designed an SC integrator. I used PAC to find the gain and I got it. How should I get the bandwidth of the circuit. In Kundert's paper about simulating SC filter, he mentioned on page 15 to use PXF analysis to find the bandwidth. It did not work for me. Any idea how can I find the bw?
  13. U

    PICkit able to prgram PICDEM2?

    pickit 3 with picdem2 Hi, I bought PICDEM 2 Plus without understanding that i need a UCE or ICD. I was searching ebay and founf PICKiT2 clone. Is this clone able to program the PICDEM2 board? or I need some ICD2? please help urgently
  14. U

    help in PAC simulation

    Hi, I need help in PAC simulation. I designed an ideal integrator and you can see the results of transient analysis show that gain is 1. However, when I find the gain by PAC simulation, I get the get of 0.5. I put pacmag =1 in vsin source with the gain of +0.5 and -0.5 to the both input...
  15. U

    Any reference abt opamp power contribution in pipelined ADC

    Hi, I am looking for a paper or article which shows that opamp power is dominant in the pipelined ADC design. It seems to be a well stated fact but I am looking for some numbers etc that how much power is consumed in what circuit inside ADC. It will be rough estimation as exact values depends on...
  16. U

    MIM capacitor mismatch

    mim mismatch Hi guys, How much MIM caps match each other? I read some where its around 0.1% for 1pF cap. Does anyone have any paper etc regarding this? I am using TSMC 0.18um, so can I find any info from the foundry and how? Regards,
  17. U

    Minimum Capacitor value in 0.18um

    Hi guys, Just wondering what could be the minimum value of capacitor we can fabricate on chip. It must be limited by the mismatch. Someone told me its around 25fF. Is this assumption correct?
  18. U

    simulating feedback opamp

    mosfet positive feedback schematic Hi guys, please refer to the figure. I might be making some basic mistake. I am using the ideal opamp in a unity gain configuration. In the unity gain configuration, the output is connected to negative terminal, however I am taking the output from the PMOS...
  19. U

    simulating switch capacitor resistor

    Hi. I am simulating the switch capacitor circuit to realize a resistor (say). The operation is as follows: On phase phi1, V1 is sampled across capacitor C. The next overlapping phase phi2, V2 gets sampled. The difference of these voltages causes the current flow. Its all quite simple. When I...
  20. U

    IBM-10/100 FRU 34L1209 reqd.

    fru 34l1209 Hi, Any have has IBM-10/100 FRU 34L1209 lan card driver....I am unable to find it for free download... thanks in advance

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