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  1. J

    Please check if the following code is correct

    Otherwise you can check my other post CONNECTING SRAM , CAMERA MODULE , PIC AND FPGA Added after 4 hours 20 minutes: well i think its working, changed my sram things are looking up, touch wood.....
  2. J

    Please check if the following code is correct

    Thx for checking guys, I think the problem is when I simulate the code inside my top it clashes with the inout and the output signal. Check the pics
  3. J

    Please check if the following code is correct

    I am actually using an actel device... Hmmm thats strange that it worked fine on yours Ill try again to simulate. Thx for the reply
  4. J

    FPGA bank voltage change on the fly...

    Hi I am using a Actel FPGA, I'm setting my banks directly to 1.5, 1.8, 2.8 and 3.3 using the allocated pins on the banks. J
  5. J

    CONNECTING SRAM , CAMERA MODULE , PIC AND FPGA

    I have also checked my net list to see if there are irregular hardware assignment although i am very net to checking the net-list but they seem fine to me, buffer placements are correct, tristate and bi directional are also correct. Can I be synthesizing the the vhdl wrong then compiling wrong...
  6. J

    CONNECTING SRAM , CAMERA MODULE , PIC AND FPGA

    HI Thx for replying, I am having a problem with the bidirectional bus for the sram I have implemented. I am using an actel device with synplify pro. When I load the vhdl code onto the fpga, and measure at the sram signals with my logic analyser I see the logic moving for my write section of...
  7. J

    Please check if the following code is correct

    The following code is an IO data flow controller for to and from sram and FPGA. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity dataflow_control is port ( state_enable : in std_logic; output_enable : in std_logic; camera_clk : in std_logic; readclk ...
  8. J

    CONNECTING SRAM , CAMERA MODULE , PIC AND FPGA

    Hi Guys I have been developing code for better part of the last couple of months as well I only learned VHDL in the last couple of months to connect a omnivision 0v5620 to fpga controlled by a pic (for the sccb of the camera) and connected to sram. I have basically tried everything but my code...
  9. J

    simple vhdl sram code to test sram chip

    simple vhdl sram code Hi , Can anyone be so kind to give me some very simple sram vhdl to test my sram chip, I have been writing code for two weeks while thinking my sram is working just to realize that im not actually reading from the sram but from the last info in the data register. Feel...
  10. J

    Omnivision SCCB Protocol

    HI Thanks for the reply... I am building a camera system for a small satellite using a omnivision camera and some peripheral memory. That sccb gave me a couple of headaches but i sort off managed to complete the transmit section which I think will be sufficient for my project as I only need...
  11. J

    USb Host controller, Vinculums VDIP1

    Anyone .... :( I managed to get it to work in uart mode, but in fifo mode its seems dead.
  12. J

    comunication between vdip1 and pic18f452

    FTSOLUTIONS !! I see you have worked with the vdip in fifo mode in the past, Is there any special trick to getting it to work, ie custom pin grounding etc. ? The module seems to work in uart mode, finding my flash and be able to be boot loaded from flash but for the fifo mode the leds up after...
  13. J

    USb Host controller, Vinculums VDIP1

    Come on people I know there is someone out there who has worked with this module???
  14. J

    USb Host controller, Vinculums VDIP1

    Hi Guys, Have any of you tried to interface a fpga to the VDIP1 module made by Vinculum. I'm trying to interface in parallel fifo mode but their documentation is a bit light. Thx
  15. J

    Omnivision SCCB Protocol

    Hi, Yes thx for the reply. I wrote the SCCB protocol in VHDL which seems to work when I do a write but I am having trouble reading from the camera module. So my problem is not the actual protocol anymore but my lack in vhdl experiance. Did you do a camera project??
  16. J

    Need help for interfacing FPGA with SDRAM (MT48LC8M16A2)

    Its just sometimes easier spending some time reading the data sheet and writing your own code. Its harsh but true
  17. J

    read cycle of a bit bang i2c, need some expert advice

    Is there no on out there that can do i2c bit bang
  18. J

    read cycle of a bit bang i2c, need some expert advice

    Hi I wrote some code for i2c and it works great write up to the point where i need to read information. The following code will start with start command >> address(read) >> command of register of interest >> another start command >> address(write) >> actuall reading of the register >> finally...
  19. J

    Reading a byte(bit) from Inputed(PortA/B) pins

    go to the forum of ccsc, there is a code bin go check there, you might be able to find code there or atleast code that will push you in the general direction. good luck
  20. J

    USB GPS interface to FPGA or Microcontroller

    Hi Experts please correct me if im wrong in the following. For the fpga to read and write to a usb device you need a host controller availible, as core i think at opencore.com or you can use an asic device from fdti :vnc1l-1a . On the website of fdti there are application notes on pic >> Usb...

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