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I have also checked my net list to see if there are irregular hardware assignment although i am very net to checking the net-list but they seem fine to me, buffer placements are correct, tristate and bi directional are also correct.
Can I be synthesizing the the vhdl wrong then compiling wrong...
HI Thx for replying,
I am having a problem with the bidirectional bus for the sram I have implemented.
I am using an actel device with synplify pro. When I load the vhdl code onto the fpga, and measure at the sram signals with my logic analyser I see the logic moving for my write section of...
The following code is an IO data flow controller for to and from sram and FPGA.
entity dataflow_control is
state_enable : in std_logic;
output_enable : in std_logic;
camera_clk : in std_logic;
Hi Guys I have been developing code for better part of the last couple of months as well I only learned VHDL in the last couple of months to connect a omnivision 0v5620 to fpga controlled by a pic (for the sccb of the camera) and connected to sram.
I have basically tried everything but my code...
simple vhdl sram code
Hi , Can anyone be so kind to give me some very simple sram vhdl to test my sram chip, I have been writing code for two weeks while thinking my sram is working just to realize that im not actually reading from the sram but from the last info in the data register.
HI Thanks for the reply...
I am building a camera system for a small satellite using a omnivision camera and some peripheral memory.
That sccb gave me a couple of headaches but i sort off managed to complete the transmit section which I think will be sufficient for my project as I only need...
I see you have worked with the vdip in fifo mode in the past, Is there any special trick to getting it to work, ie custom pin grounding etc. ?
The module seems to work in uart mode, finding my flash and be able to be boot loaded from flash but for the fifo mode the leds up after...
Hi, Yes thx for the reply.
I wrote the SCCB protocol in VHDL which seems to work when I do a write but I am having trouble reading from the camera module.
So my problem is not the actual protocol anymore but my lack in vhdl experiance.
Did you do a camera project??
Hi I wrote some code for i2c and it works great write up to the point where i need to read information.
The following code will start with start command >> address(read) >> command of register of interest >> another start command >> address(write) >> actuall reading of the register >> finally...
Hi Experts please correct me if im wrong in the following.
For the fpga to read and write to a usb device you need a host controller availible, as core i think at opencore.com or you can use an asic device from fdti :vnc1l-1a
On the website of fdti there are application notes on pic >> Usb...