Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have designed (Nmos input current mirror o/p stage) Folded cascode signle ended stage, after doing simulations i have observed different issue like
it can operate over Vcm of 0.75 to 1.8V (as supply vltage is 1.8V)
with this Vcm i am varying Vdiff also to make sure till what value all...
In Hspice how to use .ALTER and .INCLUDE statements to change the model files of slow, fast and normal corners
i know that if i use .LIB statement to include the model file
it can be changed by first using .DEL like below and .DEL with proper one
.LIB "file1" TT...
which simulations to do
how to obtain below charteristics of 2-stage Opamp (uses current mirror load)
1) Small Signal openloop Voltage Gain (Av)
3) Openn loop o/p Voltage Swing
meaning what simulations to be done ? how to calculate?
I am new to analog field simulations using spectre, SoCan anyone help me by providing spectre or spectreMDL statements or way how to obtain below charteristics of 2-stage Opamp( assume v. simple i.e mentioned in allens & holberg page 278)
1) Small Signal...
is there any formula to compute IO grid information(dimention) depending on M1,M2 and VIA1 VIA2 ..etc DRC rules ?, if so please do let me know the formula which governs the X-axis and Y-Axis IO grid values ( some times these two may not be same rite)
thanks & Regards
i am using BISIM3v3 level -11 model parameters and i could not find parameter "phi" in Spectre model parameter manual
i know that in SPICE it is termed as "PHI" and directly available
VTH = VT0 + gamma * ( sqrt(phi - VBS) - sqrt(phi) )
can anybody confirm is this parameter is...
Can any body give me an idea on how to derive a required VCM(common mode Voltage) , i am just desining based on "Andrea Boni" IEEE paper method where in i just used 6 transistors 1NMOS for tail current source and 1 PMOS on top as a current source , middle 4 NMOS as a current...
rpo od tsmc
can anybody tell me what these layers meant? and specific requirement for TSMC library for resistor creation from layout or fab process perspective
layers: RPO , RH , RPDMY
i know that these RPO along with RH is used for salicidation (to reduce resistance), where...
i understood ESR is nothing but effective series resistance(inherent) of an capacitance , it is same for NMOS realized capacitors
can anybody know how to extract ESR of an NMOS CAP?
what analysis needs to be done on this to get accurate ESR value in SPICE?
(i feel it may depend on...
Can anyone has an idea why PMOS canot be used as a CAP?
when i did rough simulation taking PMOS and NMOS of same L and Wp= 2*Wn i found that PMOS is giving more CAP value say if NMOS has value 0.13f the PMOS is having 2f
could anybody give idea on this why NMOS and NMOS in NWELL caps...
I would like to do an analysis on NMOS-CAP attached herewith what i try to do is extraction of DC capacitance that is viewd between terminals N1 and N2
can anybody suggest type of analysis to be done to get proper CV and IV characteristics in SPICE?
moreover for a good NMOS...