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Typically ESD diodes to ground will be n+ in Pwell, but in a process with native option n+ in psub without the Pwell implant is an alternative.
This can have lower junction capacitance so would seem useful for a lower capacitance ESD diode.
Are there any disadvantages for these diode types for...
DECIMM ESD simulation tool
Anyone tried this simulation software?
About the Book - ESD Design for Analog Circuits
(No connection with angstromda)
 Just corrected name in title.
I'll take the silence as a no...
Anyone seen any information about how MOS mismatch changes vs temperature?
For a circuit with trimming or calibration this can be important.
I found one source which claims matching improves at higher temperature but I would be interested to know if this has been found elsewhere...
mismatch with backbias?
Anyone got any information on the effect of backbias on mismatch? I have a circuit which is varying more than expected. The foundry model doesn't take the effect of backbias on the mismatch, which could be part of the problem. I found a few papers which showed mismatch...
LTspice has recently been upgraded to support multiple threads. I've never got round to trying this simulator but will give it a try soon.
Mike Engelhardt of Linear Tech says the intel i7 is currently the fastest processor for LTspice - it can be 2x compared to a quad core.
Anyone tried the i7...
In the instructions for the Windows version of Hsim it says Hsim should be called from a unix shell, not a DOS command prompt.
Which unix shell that can run in a Windows environment would folks recommend for ease of use/installation etc?
I am trying to track down some recommendations about gate lengths to prevent shifts in nmos transistor parameters vs Vds for 0.25um & 0.35um.
In the past I have come across tables from the foundry but I can't find any such information at the moment.
From memory I think the effect is worst when...