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Search results

  1. A

    to meet timing without chainging RTLs

    What is the different technique to meet timing when timing fails without chaing the RTLs?
  2. A

    Wrap around point of wrapping burst

    What is the wrap around point in a wrapping burst?
  3. A

    How demanding is the experience for working with PCI Express?

    How demanding is the experience in working with PCI Express?
  4. A

    What are a high speed interface and PHY?

    1. What is high speed interface? What does it mean? How demanding is the experience in working in high speed interface in VLSI industries?What are the companies who are pioneer in this? 2. What is PHY? How demanding is the experience in working in PHY in VLSI industries? What are the companies...
  5. A

    Work value of PCI Express

    How is the demand of working in PCI Express?
  6. A

    document on power gating

    Can anyone provide me a good document on power gating?
  7. A

    provide the necessary circuit

    Can u provide a circuit that can test whether a given binary no. is power of 2?
  8. A

    What field one should work?

    Which field one should specialize for his career after having 1.5 yrs. experience in synthesis ,for ASIC 1yr. in RTL Checks using spyglass and 1 yrs. exp. in Design?
  9. A

    Can anybody provide me a basic document that discusses prliminaries of FIFOs

    Can anybody provide me a basic document that discusses prliminaries of FIFOs ?
  10. A

    advantages and disadvantages of synchronous reset and asynchronous reset

    What are the advantages and disadvantages of synchronous reset and asynchronous reset?
  11. A

    gate level simulations

    Hi What are all the reasons to do gate level simulation? Is it only to see if gate level circuit is functionally operating or not because of the reason though the RTL verification shows the RTL to be working functionally but the gate level may not work functionally because of error in...
  12. A

    differnce between by formal verification and Logic equivalence checking

    Is formal verification is same as Logic equivalence checking (LEC) for which the tools are formality by Synopsys and Conformal LEC by cadence.
  13. A

    Wrapping burst in AXI

    What is wrapping busrst in AXI? How does it operate?
  14. A

    default in case statement

    Hi Suppose in a case statement all case options are provided and a default option is also provided. Will the synthesis tool ignore this default or take care of this default while synthesizing? What about the simulator? Will the simulator tool ignore this default or take care of this default...
  15. A

    About type of papers in SNUG

    What papers are accepted in SNUG? Is it that they only accepts research papers that only shows something innovative or new? If not, what elso di they accept? I think general description of a topic is not accepted. Is it?
  16. A

    Looking for documents about VLSI, Digital System, Digital Design and Analog Design

    Can you provide some sources where we can look for good documents to learn many aspects of VLSI, Digital Systemd, Digital Design, Analog Design? I sometimes come across issues for which I look for documents. Are there some website where we can look for such documents.
  17. A

    SOC synthesis with paths failing

    In a SOC synthesis if it is found that some paths are showing timing violation, what should we do for those paths then? What are the relavant design compiler commands.
  18. A

    websites containing documents are not accessible

    Long ago there were Xilinx websites which were accessible to access documents on different types of divide by counters including fraction divisons (divide by 2.5, divide by 4.5 etc.) and also there were documents of FIFO. Those inx websites are not any more accessible. Can anyone provide me the...
  19. A

    FIFO architecture and flipflops

    I know how FIFO is realized by DPRAM. But FIFO is also realized by flipflops. Can anybody provide me a document that write about how a FIFO architecure looks with flipflops or explain about this id you do not have any document? I had a document on how FIFO architecture looks with DPRAM. Please...
  20. A

    ASIC vs SOC AND vs FPGA

    What is the difference between ASIC and SOC? What is the difference between an ASIC implementation and FPGA implementation structure?

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