Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. D

    ADE XL switch view list for simulating verilog functional code

    I have run into a problem with simulating a verilog code in ADE XL window. Here are what I have done so far: Created a new cellview, cellA, and chose its cell type as Verilog and its cell view as functional under Library myLib. By clicking OK a text editor popped up, then wrote down a simple...
  2. D

    Post simulation of back-annotated pnr netlist does not work

    I'm facing a problem with a post-pnr simulation. I know the question has been asked several times out here but I have not found the answer yet. I did post-synthesis with DC compiler, my timing constraints were met and the simulation of the netlist+SDF works as expected. I did PnR with Innovus...
  3. D

    Timing analysis accuracy when MMMC definition file not given RC corner

    I want to configure my mmmc definition view file such that only a single mode single corner analysis to be defined. For the current design I have given only technology and standard cell LEF files. In the mmmc browser there is a section called RC corner in which a cap table is required to be...
  4. D

    How to tell the sdf_annotate() which delay it has to annotate my design with?

    I have written a tcl file and to the link library added only a fast.db file. Now suppose I include a second db file but this time a slow.db to my tcl file. Now in order to simulate the gate-level netlist with sdf back-annotation delays how should I choose the fast or the slow delay I defined in...
  5. D

    Double-delay inverter and its non-linear delay transition

    I have a double-delay inverter chain as shown in the image. The actual purpose of this inverter chain does not matter for the sake of this question. Each double-delay inverter is formed by parallelizing two small and large inverters. The small inverter can be turned off by a gating control...
  6. D

    post synthesis simulation methods for power estimation

    I am trying to do my first digital synthesis design using design vision. I have got a question along the way. There are two methods to estimate power consumption to my knowledge: First method comes directly after the synthesis is done; while we are in the Design vision we go to the Attribute...
  7. D

    Effective resolution and dynamic range (of ADC)

    Do effective resolution and dynamic range describe the same thing? Per my understanding, the effective resolution and dynamic range are defined as the ratio of the full-scale input range to the RMS input noise, including both the intrinsic and quantization noise. The only difference I found was...
  8. D

    Which LSB unit is chosen for DNL/INL measurements? Ideal or measured LSB?

    The DNL/INL measurement in the following exemplary 3b ADC shows different results depending on which LSB unit is chosen. For the case of the Actual_LSB unit we get DNL=0 and INL=0 for all codes. This tells me that the actual TF has no linearity errors! However, for the case of the Ideal_LSB unit...
  9. D

    [moved] Generate two signal tones with a frequency offset (on-chip)

    How to generate two frequency tones with a 500Hz frequency offset from a single 26MHz crystal oscillator? Because that is part of an integrated circuit we cannot use signal generators and so only have to make these on chip. Any ideas?
  10. D

    [SOLVED] ADC DNL/INL measurement prior to calibration

    In the following image the actual transfer function falls off because of the negative gain error. What usually is done in software is to compensate for the gain error using best fit line method or other ones as per the designer and the application requirements. I am working on an ADC where...
  11. D

    Sinusoidal pulse position modulation for TDC simulation

    I am testing a time to digital converter to measure its dynamic nonlinearity. The TDC takes as input two signals and calculates the difference between their rise edges and represents the result in digital format. For that purpose I need to generate two input signals whose timing difference...
  12. D

    [SOLVED] Cancelling gain error of an ADC

    I have read that in order to measure the DNL/INL errors of an ADC one has to nullify the gain and offset error. It's simple to compensate the offset error by shifting the curve either in the x or y direction. However, the gain error compensation is less obvious to me. How do you usually correct...
  13. D

    SAR ADC switching energy calculation

    I am trying to calculate the switching power needed when moving between different switching positions in a capacitive DAC. The image below depicts the energy needed to go from a certain position to another for a conventional capacitive switching DAC. For example, in going from state A to B the...
  14. D

    Issue with SAR ADC design

    The image below is a monotonic capacitor switching SAR ADC. The positive differential input Vip is connected to Vref, and the negative differential input is connected to voltage Vn. The goal is to find out Vn/Vref. The tricky thing however about the design is the reference voltage Vref, which is...
  15. D

    dynamic two stage comparator

    In the following dynamic two stage comparator transistors Mx are used to connect the pre-amplifier stage to the latch stage. But are there any other purposes for Mx? In a well cited paper it was claimed that the transistors were used to provide a delay for the latch stage. They also added that...
  16. D

    Settling time of ADPLL

    I am reading a paper which has proposed an ADPLL with a custom 8b TDC. Throughout the TDC design it claims the following: So how can a wider dynamic range make difference in the robustness of the settling time?
  17. D

    Non-linearity analysis of time to voltage converter

    How can I measure the linearity of a time to voltage converter? For ADC we can measure its DNL, INL, gain error, ENOB etc. to assess its linearity performance. But as for a TVC both time and voltage vary continuously it does not make sense to define DNL/INL and so on. So what are the alternative...
  18. D

    Time domain jitter analysis in cadence

    I have a made a ring oscillator using inverters connected in series. The output of the chain is connected to the input through a NAND gate. Lets say there are N of these inverters, so we have N outputs. Because of the mismatch and jitter in the devices the output phases will be slightly changing...
  19. D

    CMOS inverter mismatch and jitter analysis

    I want to work out the probability density function of a single inverter in case of mismatch and device jitter. This paper (https://ieeexplore.ieee.org/document/7063035) considers a long chain of inverters and writes the following equations to describe the stochastic nature of the inverter...
  20. D

    How to make an inverter less sensitive to PVT variations?

    I am trying to use a couple of identical inverters in 0.18um TSMC technology. For the lowest propagation delay I ran a Monte Carlo simulation for a single inverter, where I got ~1ps for the std of the propagation delay, and roughly 13ps for the mean delay. Now if you compute 6*sigma value you...

Part and Inventory Search

Top