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System Verilog IS in my opinion already now Nr.1. It is sw vendor independent and thus sw vendors are very motivated to offer bunch of helpful libs for free.
(See AVM from Mentor - supported SV and SystemC, recently OVM from Mentor and Cadence - supporting just SV(!))
I would not recommend to...
what is cworst and rcworst
r,rc worst and best are used to mimic better process variation of parasitic C and R in .13nm and below additionaly to slow,slow and fast,fast transitor variation in the simulation. Motivation is to get better yield.
Right. I was faced with the similar problem with Astro Rail too. Hierarchical power analysis simply gave a wrong results. I had to flat the design to get the right numbers. BTW have you used top level .sdc to define the clock activities and have you propagated them through the whole hierarchy ?
IMHO all modern routers including nanoroute in SOC are channelless ones. It is true, that old channel routers were fast. .13 and .09um technologies need a flexible routers which are supporting all their specific DRules
Re: What is Max Frequency of the commercial ASIC u hav desig
Are those who mentioned 500MHz and above still using classic synthesis, usual clock tree balancing and .lib based timing analysis ?
Re: Pls help on Fortran
0. , 1. in the expressions would mean real number representation.
num(i) = 1. <=> num(i) = 1.0
It means the array num() contains real numbers. In case o integers you would see:
numi(i) = 0
Well, I would suggest you try to start at the small company. In my opinion you should have an opportunity to be somehow engaged in all parts of the flow. I mean from the specification through the front end ,through the testability, backend, assembly, device test and production yield tuning. You...
Re: Backend flow
If you take a First Encounter Tutorial, you will see the example of a typical flow.
I would recommend you to use magma, if you have access to it. If not try to keep you flow simple. Btw I have seen the request for the spare parts in different chips, but I have never seen that...
Re: Are you satisfied with design service/ASIC house's die s
Well, you get the size of your chip AFTER you do the layout. So the quotation is always based on the estimation and therefore must be conservative, otherwise the design house will bankrupt. If you want to have control over the chip...
It is possible to simulate very large netlists in HSIM, therefore you need not probably do the mixed mode simulation. The flow is:
Translate your Verilog netlist to the transistor one. v2s is ok for it
Include your libraries in the top level circuit.
Re: How to remove spikes?
Usual method is to store the outputs to the output register. The glitches can not propagate through the register stage. To be a little bit "analog" you may also decide to use dynamic logic instead of the static one you are using now ;-).
Re: ture random number generator based chaotic design help m
I would suggest to use several ring oscillators, where the inverters are done by the weak transistors. The thermal noise will produce a jitter. Assuming you have 4 of them where the typical middle frequency of each oscillator is the...
silicon ensemble uses rules described in "technology".lef. Simply look all LEFs which you read in. There is described e.g. the metal width, pitch, via rules. The rest has to be done in Silicon ensemble itself. So you need also a verilog netlist and the abstract blocks (LEF) for each primitive...
You have to find the operating conditions under which your chip is working. You have your test, you specify the operating voltage range, temperature range and create so called schmoo plots (characteristics where you can see in which areas all your tests passed and where they failed), you perform...
You have to be more specific. If your 8-bit numbers are in 2's complement, the multiplier will
differ from those for multiplication of positive numbers. Multiplier and their different implementations were often published in IEEE Journal of Solid State Circuits. If you do not
targetting the high...
It depends on how your chip is designed. If you have just flip-flops and use asynchronous reset
for each of them, you need just one clock period. You have to keep in mind, that reset has not to go inactive close to the active edge of a clock. You have to guarantee, that all your chip
Re: half bit delay circuit??
Assuming following data stream:
11111100001111110 input data
01111110000111111 input data delayed about 1/2 period
Where is your clock ? :?
If you are generating also the input stream, you should use a suitable code like...
Re: half bit delay circuit??
It seems to me that you want to have half bit delay to guarantee a good sampling point for your
(probably high speed) random bit stream. :wink: Are you sure your data stream is not scrambled ? I mean the 1/0 distribution is really random ?