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    sapartan 6 configuration

    i use spartan 6 xcls4 - on my board SUSPEND is floating while i use serial slave configuration, in ise help i found that i can PULLDOWN this pin but this optiona ctually isn't found on the toool itself, what is the effec of this pin and how can i overcome this issue
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    bit and bit vector using in vhdl

    hello, r bit and bit vector synthesisable in vhdl
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    Cypress ucontroller code development

    Any one know how to edit cypress CY7C68014A-56LFXC Interface, i have code but cannot find how to edit pins, i just want to swap 5 pins how can i do that
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    Decoder datasheet is required

    i want 1 output input signal selected by 3 selection lines is multiplexed to 8 different outputs, i know that Decoders make that but i couldn't find any datasheets for that can anyone help
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    Is there is interfaces support up to 80 MSPs

    I want to take Samples upto 80 MSPs during this period i want to make processing and send data to PC ? can i do that is this rates in FPGA, Interface with PC
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    I/Os Voltage values and delays in any FPGA

    What is the relation between (Vdd) I/Os Voltage values and delays in any FPGA, Is that increase Delays ? Why? and How i choose the best I/Os of FPGAs to optmize delays ??
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    What are the differences between : DCM, PLL, MMCM and PMCD

    what is Differences between : DCM, PLL, MMCM and PMCD i only know that all generate clocks
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    using use ieee.std_logic_signed.all; and numeric ??

    which better when usign (+) addition in a code
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    C/Cs equation or transfer function on matlab

    on my grad project i stopped at following Have the following Rates of Dynamic System (something moving on air) Vs time of this sampled rates How to define Transfer function of it by MATLAB, considering it is 2nd order or 3rd order + delays considerations :) - - - Updated - - - and how to...
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    Need step by step manual on Design Compiler setup

    Hello, i dun use Ubunto but put it to run dc program how can i install dc in steps :)
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    Topd Down vs Down Top design in vhdl

    Topd Down vs Down Top design in vhdl What is the difference :arrow:
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    FSM toolbar in Modelsim

    Modelsim never understand my FSM how can i write it in a way MODELSIM can understand :-(
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    Need help with transfer function in VHDL

    I am implementing a control system in VHDL. Now I am facing a couple of problems. For the controller itself, I used two inputs - error and change of error. Now I have to pass the controller output to a plant which has the transfer function of 1/(ks^2+s), where k is a real number. I don't know...
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    i never used inout and buffer in vhdl but i dunn know when to use them and what is the differences between and what is them :D ??
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    tutorials to learn Microcontrollers

    I want to make a project using microcontrllers recommends to fast learn that (using C)
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    read data from analog signals into PC

    something i couldn't imagine how to do simply, i can use vhdl with fpgas but i dun know how to use that in this mini project readings from analog signal comes from a detector have to read it on PC how to do that with simple sparton 3e kit !! and how to do it with a board that owns its DAC...
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    vhdl port instantiation types

    what is the difference between instantiation with writing a component, with declaring the architecture , with just wriring entity work.entity_name can you please write the correct declaration of e
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    type declarations in vhdl

    How differ in use , in synthesize in debugging or in anything type matrix IS array (0 to 3) of std_logic_vector (7 downto 0); & type row is array (7 downto 0) of std_logic; type matrix is array (0 to 3) of row;
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    Connecting 2 boards with wires

    hello, i have this problem i want to communicate two xilinx fpga of type sparton 3E with 5 signals (wires) the two boards have the same clock .. the communication between them through 1 data wire and its enable and 2 other data wires and their enable how to synchronize 2 clocks without addition...
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    Problem in Utilization Area

    my Utilization is about 80 % not maped although the slices not mapped are reported to be not large ( = 1% of remaide area) i have ths question If i have an entity consists of many components how can i know utilization of each without making each compoenent as a top level in ISE xilinx

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