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    how to solve the problem: if setup time is not enough?

    I said I need to use PLL which made the interviewer very unhappy...:) Maybe there's a way which I don't know.
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    how to solve the problem: if setup time is not enough?

    HI, it's an IC interview question, can anyone give me a perfect answer? When your design's setup time is not enough, what will you do? How to design a 5.5 frequency divder with some simple CMOS transistors?
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    what dose it mean -- Fading and erosion?

    I heard a lot of guys say the words regarding DSP system, can anyone explain them? fading? erosion?
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    Help --- What's "unscreened balanced pair"?

    I thougt they are just a pair of wires without metal screened or sheltered.
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    BGA soldering in series production

    Let me know if you want know the best PCBA companies in China. And I can help to to contact and negotiate
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    sorry info is not available

    Help on Verilog floating point generator solution 1: opencores solution 2: Synopsys module compiler Solution 3: Perl script (by yourself)
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    How to subtract a binary A by 3 (A-3)?

    subtract 3 learn a little bit verilog or system-verilog, let syn or sim tool to do the job, you can just "-" to write your code.
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    specman basic training

    Specman is not easy for self-learning, you need a formal training and excercise your abliity in real project.
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    how to generate *.syn file

    *.syn file contains RTL hierarchy and used for DC synthesis. It's error-prone to write it manually.
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    How to set VCS working directory

    hi, Thanks Ajeetha! I have solved it, the file should be kept in the same dir where the top module is.
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    How to set VCS working directory

    my codes need to read a vector and I put the vector file in the codes folder, but when I compile it with VCS, it always told me: How can I do to solve it?
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    Problem with segmentation when using VCS

    Problem in using VCS $vcs -debug -f file.v if file.v is a verilog file list, you have to use '-f' to tell vcs you want to compile it instead to treat it as a verilog file.
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    Booth algorithm hardware implementation

    booths algorithm example Thanks uditkumar1983 and lever! Hi, deepu_s_s, I am willing to share your design if it dosen't has any issue with IP sensitivity or confidential.
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    Booth algorithm hardware implementation

    algoritm booth hardware my problem is: 1. can anyone help to convert this VHDL to verilog2001? 2. how to design a parameterized Booth based multiplier with Wallace tree? 3. what is the performance of Booth multiplier compared with synopsys DW lib's
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    How to make a SystemVerilog Class to read a text vector

    fscanf systemverilog I do not use sv to process my text file; I just use it read the vector from the file and feed the vector to the testbenches or DUT. The reason why I need a sv class here is the class can be easily reused and called.
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    Booth algorithm hardware implementation

    booth algorithm vhdl code Anyone knows about Booth algorithm? It's great help to hardware multiplier, here I got an example which can be your reference. Also, can somebody help to conversion below VHDL to verilog? It's better to keep the parameterization and use verilog2001 syntax "generate"...
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    How to make a SystemVerilog Class to read a text vector

    system verilog read file How to make a SystemVerilog Class to read a text vector and how to sync it with the global clock? read every byte per cycle I have tried to write one but it seems not work... can anyone give me a hint on that? class #(parameter File_Name =...
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    [help]VHDL translated to verilog, hard stuff?

    Somebody help to conversion below VHDL to verilog? It's better to keep the parameterization and use verilog2001 syntax "generate". Thanks! ------------------------------------- -- Define data width -- ------------------------------------- package mypackage is constant NBITS :natural := 7...
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    What is the basic things you need for doing synthesis in VHDL?

    Synthesis basic need is to have a synthesis tool. you have many choices!

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