# Search results

1. ### THD of Pulse Width Modulated Sine Wave in Spectre

pulse-width modulated sine wave Hi, I read it from "The Designer's Guide to Spice and Spectre", that we are able to find the THD of a pulse-width modulated sine wave using the Fourier Integral method by Spectre. The book also mentioned that Fourier integral is not subjected to aliasing. Now...
2. ### Matlab Script for ADC SNR Post-Processing

adc snr matlab Hi, I have some question regarding the script I got. Part of it is as follows: . . . % Create the minimum, 4-term Blackman-Harris window for FFT pwr_win=0; for i=1:Nt %where Nt is the no. of FFT bins...
3. ### Stability of sample and hold circuit

Hi, I was wondering if it is neccessary to do a stability check on the circuit in hold mode? My thinking is that since there is a holding capacitor in the feedback loop, the loop is broken (from dc point of view). And also the capacitor is there to hold the charges and there should not be any...
4. ### How is the crystal drive level determined?

I am currently designing a crystal oscillator. From crystal datasheet, there is usually a specification known as drive level. Is the drive level of the crystal determined by the crystal or is it determined by the oscillator circuit design? Thank you.
5. ### Nature of roots of a cubic equation

I have derived a transfer function containing 3 poles. All the coefficients are positive but from matlab analysis, there is one LHP real pole and a pair of RHP complex poles. Previously, I have a misconception that a cubic equation having all +ve coeff will yield all poles in the LHP. Could...
6. ### Frequency dependency of ESR value of capacitor (for LDO)

esr for capacitor low frequency I am currently designing a LDO voltage regulator making use of the ESR value of the external compensating capacitor to make the regulator stable. It is well known that the ESR value helps to create a zero to stabilize the regulating loop. I got the impedance and...
7. ### ESR value of the compensating capacitor for LDO regulator

esr value I am currently designing a LDO voltage regulator. It is well known that the ESR of the compensating capacitor contributes a zero to stabilize the system. Right now, I have a problem, i.e. I do not know what is the ESR value of a ceramic capacitor. I cannot find any information on ESR...
8. ### Questions about Cascode Bandgap

Cascode Bandgap Hi all, I have some questions regarding the cascode bandgap. 1. Could someone please explain to me how the start-up circuit works? My understanding is that the NMOS acts as a pull-down resistor to pull the voltage at the gate of Mpinj to GND so as to inject a current into the...
9. ### Matching of long transistors

Hi, I am wondering is there any more considerations to be taken into when trying to match very long transistors. For example, I want to use current mirrors to mirror a very small current and the W/L derived is 0.02 so that the transistors are in strong inversion. I chose W to be 1um and L to be...
10. ### DNL and INL simulation time

inl r-string dac Hi, I am trying to get the DNL and INL for my 12-bit SAR ADC. The problem is that each sample takes abt 2 hours simulation time. Does that mean I have to spend 8000 simulation hours to get the DNL and INL plotted? It sounds absurd to me. May I know am I doing it the correct way...
11. ### Frequency Response of Bandgap Loop

Hi, I am designing a bandgap reference as shown below and I am measuring the loop gain of the circuit of (Vob-Voa)/(Via-Vib). By changing the size of the cascode transistor that is circled, I could get two different frequency response of the loop gain. The graph on the left is obtained when the...
12. ### Nanoampere current reference needed

1na current reference Hi, I need a nanoampere current reference that operates at a 1V supply voltage without using large resistors in megaohms. Have anyone of you ever designed one? Kindly share the information with me. Thank you.
13. ### Process variation tracking design techniques

Hi, I would like to learn about design techniques that are able to track the process variations to some satisfactory degree. Any books/papers to recommend? Thank you.
14. ### About autozeroing and correlated doouble sampling techniques

From what I know, both techniques are able to reduce the effects of offset and flicker noise of opamps. What is the subtle difference of these two techniques? Thank you.
15. ### switched capacitor sample and hold circuit

holding capacitor sample and hold Hi, I am designing a SC sample and hold circuit as shown in the following picture. When I used a large holding cap of 1pF, the output of the opamp takes a longer time to settle down at phase 1. Furthermore, the output during phase 2 seems to deviate more from...

Hi, I am now having my first tapeout and I would like to know what are the typical sets of corner simulations that designers run in the industry? From what I know, there are typical,fast and slow PMOS and NMOS models; high, typical and low R and C; and high, typical and low temp and Vdd. If we...
17. ### Design of analog MOS switch

site:www.edaboard.com cmos switch Hi, I would like to know how to determine the size of MOS switches. From what I know, the size should be small in order to have less charge injection but the size should be large to have a small "ON" resistance. Furthermore, I have frequently heard of people...
18. ### Binary weighted capacitor array in DAC

Hi, I am currently design a 12-bit SAR ADC. I am using the binary weighted capacitor array as the DAC. I'm wondering is there a way to split the capacitor array in a way such that only capacitors corresponding to the smallest 6 bit need to match to 12-bit resolution while the larger 6-bit can be...
19. ### Hspice simulation and switches non-idealities

Hi, I would like to know whether Hspice can simulate the non-idealities like clock feedthrough and charge injection of the switches effectively. If so, how to do it? Thank you.
20. ### Noise and offset of transistors in weak inversion

Hi, could anyone please provide some materials on dc offset of transistor pair in weak inversion and the thermal noise, 1/f noise of transistors in weak inversion as well? I could only find information on current mismatch of current mirrors in weak inversion from IEEExplorer. Thank you.