Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. A

    LVS errror :BAd componenet sub type

    Hi, When i use component havar in cmrf8sf ibm130 technology then i get an error called bad component sub type D(havar) DDo(net1) When i checked the .src.net and .sp file then the instances have different order of parameters. How do i fix it?
  2. A

    On chip balun single ended to differential

    On chip balun for single ended to diff Today at 12:14pm Quote Modify Hi, I am using a balun to convert single ended signal (from signal generator) to differential (onchip). 1. Is it necessary to ground the center tap of secondary? I am AC coupling the differential. 2. Since sig gen has 50 ohm...
  3. A

    Choosing self resonant frequncy of offchip inductor

    Hi, I need an offchip inductor L= 10nH for matching LNA input @ 2.4Ghz. How do I choose the self resonant frequency? 2X 3x 4X?
  4. A

    Injection locked oscillator: direct v/s indirect

    Hi, Which method of injection is low power consuming in injection locked oscillator? 1. Direct injection where MOS is connected in parallel to the tank 2. Indirect injection where MOS is connected like a diff pair
  5. A

    choosing inductor for low power consumption of vco

    Hi, I have two inductors: L1=2nH Q1=15 Rp1 (Parallel)=450 ohm L2=4nH Q=11 Rp2(Parallel)=500 ohm where Q=Rp/Lw If I use them in VCO I want to know which one will provide low power consumption. I think Rp2 is greater and hence less -gm will be required to start up and hence inductor 2 will be...
  6. A

    PA design: issue with parasitic capacitance (bondpad+bondwire+pack pad+pcb)

    Hi, I am designing a PA as shown in schematic. Some specs are: 2.4 GHz ultra low power (<1mA) moderate linearity (modulation is QPSK, moderate PAR, either class A or class AB) The problem is my gain falls by 2dB (w.r.t mid band gain) at 2.4GHz when O/P is loaded with 200f parasitic...
  7. A

    generate bias voltage of power amplifier

    What is the best way to generate bias voltage VB1, VB2 and VB3?
  8. A

    Transient response of the vco control voltage of a PLL

    Hi, 1. I have attached transient response of the control voltage of my PLL in Cadence. This is NOT behavioral reponse. 2. From t=0 to 100us it is the startup time. No frequency step provided 3. At t=170us a frequency step of 40MHz (max size for the pll) is provided and resulting transient...
  9. A

    op amp used in charge pumps for charge sharing / mismatch

    Hi, In charge pumps to remove charge sharing a unity gain opamp is used. Again to minise current mismatch or increase resistance of current sources, a servo opamp can be used as shown in razavi books. I want to know which method is more helpful in minimising spurs? I have power constaraint and...
  10. A

    vco control voltage in pll behavioral simulation in simulink

    Hi, i simulated my pll using simulink n time domain and ended up with peculiar control voltage even with 60 deg/75deg PM. Fig 1 shows the output of loop filter. Fig. 2 shows output after VDD saturation. I want my vco control voltage to slightly rise from 0 at t=0 and settle as if critically...
  11. A

    simulating mim cap and diode varactor combination for lc vco

    Hi, a) I am designing a LC vco and using the varactor shown in fig. 1 where C is mim cap and C2 is diode varactor Resistor sets the node V1 near 0V. b) I want tuning range from 786Mhzz to 800Mhz which requires C to change from 1394f to 1342f i.e. delta_C=52f My doubts: 1. How C1 and C2 and...
  12. A

    PA required for -10dBm o/p power

    I am designing a transmitter with o/p power of -10dBm. This translates to a peak to peak voltage 200mV. Is there any necessity of power amplifier if the O/P is available from a LC oscillator capable of generating such Vpp=200mV
  13. A

    Low power transceiver design

    Hi, I am working on a low power transceiver for Wireless Body area network protocol. How do I get the phase noise specs of my PLL from the protocol specs. The protocol specifies the transmitter specs like EIRP, transmit mask etc. and receiver specs like sensitivity , ACPR etc.
  14. A

    Suitable technology for WBAN

    Hi, I am going to design a low power biomedical transceiver for wireless body area network. Most of the papers in this field use 130nm technology. But I have no idea how technology impacts low power radio performance. Can anyone help /cite references to choose the proper technology? I...
  15. A

    Is offchip decoupling cap for analog and digital ok?

    The frequency of my circuit is 30khz. Analog & digital has seperate Vdds but no seperate ground pins.Analog section has onchip decoupling cap of 15pf but digital has no onchip decap. Is offchip decoupling cap for analog and digital ok?
  16. A

    startup citcuit for self bias

    M1-M5 constitute startup circuit for the self bias refernce. VDD is 1.2 and V1 is usuall 700mV. M1 is sized for current=30nA. After circuit startsup V2 is 1v and M1 goes to triode, M5 turns off. Is M1 going to triode after startup a problem?
  17. A

    Layout of a very long transistor

    Hi, I have a transistor of very long length! w/l=1u/40u. How do I layout? As a single block or as a series of small transistors. Some say series is good as it will match the models well Some say at low currents there can be noise injection in the middle transistors in series connection. My...
  18. A

    Ring oscillator based ADC f_signal/f_ref ratio

    The counter in a ring oscillator based ADC counts freq_signal x pulse_width_ref or time_period_ref x freq_signal. Now if the counter is 10 bits I am wondering if their ratio should be 1024 for 10 bit resolution. If freq_signal=3khz and freq_ref=4khz, how do i make them work? Shall i use divide...
  19. A

    stabilt of beta reference

    i have designed a low power beta multiplier refernce (70nA) as shown. The opamp is a 5T diff pair.To check for stabilit i broke the -ve feedback loop and plugged iprobe from analoglib in cadence. stb analysis shows phase margin of 20 deg and gain margin of 14dB with C=2pf. I m not able to achive...
  20. A

    low power current starved ring osc

    Hi, I am designing a low power current starved ring oscillator as shown in attachment. The bias current for each inverters is in the range of 50n to 100nA. M1 M4 are in strong inversion saturation and act as current sources. i have made w/l very small like 1/40 to put them in strong inversion...

Part and Inventory Search