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    Installing vitis on a low specs-pc

    Hi, In Xilinx documentation https://www.xilinx.com/html_docs/xilinx2021_1/vitis_doc/acceleration_installation.html#vhc1571429852245, the minimum requirement for installing Vitis is 32 GB memory. My pc is a hp ProBook 450 g3 i7 6500 with an 8 GB RAM DDR3. Would I be able to synthesize...
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    [SOLVED] Initializing Xilinx BRAM with image pixels

    Hi, I would like to initialize Xilinx BRAM (ROM) with image pixels, any ideas ? cheers,
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    Intialization of SDRAM DDR2 memory in Xilinx tools

    I would like to know how can initialize the content of DDR2 memory using xilinx tools ? my purpose is to load to static images to the memory before starting its operation, meaning initialzing different memory locations with different pixel values.
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    Frame buffer controller with dual_clock FIFO

    I am trying to build a frame buffer controller to control two video feeds coming from two stereo cameras simultaneously on digilent Atlys board (spartan 6). the buffer is composed of a true dual port memory with two ports A and B to store the two video feeds the data is read from either ports...
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    Monitoring different clock domains in chipscope pro

    I have a multi_clock design, Is it possible to display the different clock domains on chipscope pro tool and how ?
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    Strange behaviour of Standard dual-clock FIFO

    I'm using the Xilinx core generator to generate a dual-clock FIFO in standard read mode, the simulation in Isim shows a strange behaviour, the first two writings are skipped as indicated by the wr_data_count output can somebody please tell me what are the possible reasons for such behaviour ?
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    [SOLVED] Displaying grayscale video feed on HDMI

    I am working on a project that display the video feed of two streo cameras in RGB format using an HDMI interface on Digilent Atlys spartan 6 FPGA boad, I used a converter in order to convert from RGB24 to grayscale, my question is it possible to display grayscale video feed on the HDMI interface...
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    Communication between PC and Atlys board via ethrnet

    Hi guys, I am trying to create a loop between FPGA and pc to transmit an receive raw ethernet frame, I found a vhdl implementation of ethernet MAC core in https://github.com/pkerling/ethernet_mac. Any ideas how to test the system ?
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    Designing ethernet controller on atlys board

    I would like to use the etherent connector on Atlys board for communication where do I start from ?
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    Scaling down the resolution of VmodCam demo project, Atlys board

    Hi guys, For those who worked with VmodCam I am working on a project involving the implementation of real-time stereo vision system, for this purpose I am using the demo project provided by the digilent company to display video feeds on HDMI port...
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    [SOLVED] communication between Matlab and FPGA virtex 5

    I am trying to implement an image acquisition system that communicates between Matlab and PC, the system works as follows: first of all matlab reads a grayscale image of resolution of 512x512 where the colors are 8-bit coded, the image then is segmented into 512 segments, each of them represents...
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    [SOLVED] Interfacing UART with FPGA xilinx virtex 5, problem ?

    I am trying to design a simple loop of communication system between pc and FPGA virtex 5, for this purpose I interfaced a BRAM with uart module, I am using VHDL as the hardware description language, the memory used is a 16 byte simple dual port BRAM ram with a width of 8-bits; is supposed to...

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