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  1. S

    why p+ poly resistors are preferred over n+ poly resistors?

    Usually the sheet resitance of p+ poly is larger than n+ poly. That helps when you try to save area.
  2. S

    Opinions on All-Digital PLL design

    All Digital PLL For 45, 65 and 90nm technology, the voltage headroom is decreased. and it's more and more difficult to design ADPLL with digital core device. Beside voltage headroom, the gate-leakage is also a big problem for loop filter design. Although thick-oxide device can be used to solve...
  3. S

    How to improve LDO's transient response?

    May someone provide papers or methods about fast transient loop?
  4. S

    The pros and cons of running the power rails next to each other and below the block

    Power rails For core limited case, if VDD and VSS rails are running above and below PAD, you may insert ESD devices beside PAD and in between VDD and VSS rails. That will make the I/O cell shorter but wider. You may save some area on your I/O ring. But the Latch-up will suffer if you don't add...
  5. S

    How to get output impedance requested by IEEE 1596? ( LVDS)

    lvds specs 300ps at 1gbps OK. If you want to do the single-end termination on TX side. One of the method is to use the source follower on the driving side, and the other side you can use switching resistor. In order to control the impedance, you must design some kind of tracking ckt on the...
  6. S

    Need papers about 12b pipelined ADC

    Hi, The following papers are for your reference. Enjoy it :)
  7. S

    How to get output impedance requested by IEEE 1596? ( LVDS)

    ieee1596 If the 100 ohm termination resistor on RX side match the LVDS channel impedance, then there is no reflection from RX side. But if not, then there will be 2nd reflection on TX side, and this 2nd reflection will come back to RX. So for some high-speed LVDS transmitter (>1Gbps), the TX...
  8. S

    who use ADIT sim tool

    Hsim is better. This tool provide more capability to trade-off speed and accuracy on different blocks. But you must know your chip well in order to set the options properly. ADit doen't provide this capability. You don't know exactly how the tool group/partition the circuirt. But for individual...
  9. S

    power cut cells in ESD protection?

    esd consideration If you have sensitive I/O pad for internal analog circuit, you may need to cut the I/O ring into 2 sections. One is for digital I/O and PWR/GND pads, the other is for analog I/O and PWR/GND pads. Each section with their own vdd1, vdd2, vss1, vss2,.... The reason for this is to...
  10. S

    please tell me some papers about the cmfb stability

    The presentation slide for the above paper.
  11. S

    What's the main criterion for choosing number of stages in a ring oscillator design?

    ring oscillator Hi, In terms of power and speed, less stage is better.But usually VCO gain of less-satge design is larger compared to more stage design. In terms of VCO phase noise, we don't want VCO gain too large. Another consideration is more-stage VCO is more sensitive to power-supply...
  12. S

    How to size BJT for BGR design...

    Hi, Usually, the BJT drawing size provided by foundary is used for design due to modeling accuracy. As for BJT area ratio of the PTAT part, it depend on the offset voltage of the OPA used in bandgap. If you want to have small statistics deviation of your 1.25V output during production, you can...
  13. S

    One question is about CMFB in folded-cascode OPAMP.

    In addition to all process corner, temperature and voltage variation, remember to consider bias current variation. So the simulation of total combination should be; 5(process corner)x2(-20C,100C)x2(3V,3.6V)x2(bias variation)=40. That will guarantee your yield !
  14. S

    How Linux PC check-out license from UNIX lic server

    linux license check Thanks : ) It works well now.
  15. S

    How Linux PC check-out license from UNIX lic server

    how to check tools license in unix Dear Sir, i have the following setup issues, i need some one to help me out . we plan to install license on sun workstation, the license is floating, but we plan to run the real simulation program on faster PC with RHEL AS3.0 OS installed. The actual...
  16. S

    SPICE & PSPICE: accuracy?

    It depend on what technology you plan to use for your design. If 0.18u, 0.25u is your target process, the MOS model may be a problem due to lack of MOS model support in PSpice. If 0.5u, 0.8u or 1um technology is your target prcoess, it should be OK. I knew that some power-management fabless...
  17. S

    doesn't hsim have a graphical interface ?

    You may use SpiceExploer or CosmoScope to view the waveform in Linux. Nassda used to bondle OEM waveform viewer of nWave from Springsoft before.
  18. S

    Why clocks have 50% duty cycle in many designs ?

    Clocks problem If possible, the design style of digital logic with only one edge trigger F.F.(either rising or falling-edge) is preferred for one clock-domain synchronous logic design. That's more robust and reliable, and you don't need 2X frequency PLL. That saves power, and CTS is also easier...
  19. S

    What different betw. input pad with & w/o schmitt trigge

    Hi, Because of the hystersis characteristic, the delay from input to output of schmitter pad is a little bit longer than normal input PAD. But the difference should be small if the rise time of input signal is small. Hope it helps : )
  20. S

    Synopsys Closes Nassda Acquisition

    Too bad :( Hsim will cost more than before :(

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