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  1. L

    multi-voltage synthesis problem

    Hi ThisIsNotSam, sure, for debug timing issue, reported same path on both method. method_1: kindly refer to attached method_2: kindly refer to attached Many thanks.
  2. L

    multi-voltage synthesis problem

    Hi navpics1, Per your suggestion on method_1, Method_1: synthesis whole chip top-down : read_rtl load_upf : current_design chip_top : compile_ultra compile_ultra compile_ultra -scan -no_autogroup : Timing violation, on same path for example, improves 0.2 from -12.11 to -11.09 Really...
  3. L

    multi-voltage synthesis problem

    Hi ThisIsNotSam, thanks for advice per your suggestion: load_upf did not show any suspicious message in either case, neither error nor warning found. and number of level shifters are the same in both cases. While failing path of timing violations did not cross domains, all start and end...
  4. L

    multi-voltage synthesis problem

    Hi, Apologize for not proving details at the first time. My design, chip-top, containing 2 major sub-module, A & B. Whole chip is in 5V power domain always on except module A is in 1.5V and It can be shutdown for saving power. Foundry provides two sets of Std. cell: 1.5V base. 5V base...
  5. L

    multi-voltage synthesis problem

    Hi I'm doing multi-voltage synthesis with upf with no luck since timing violations are huge.. the strange thing is if I use buttom-up method, say synthrsis submodule A first and set dont_touch on module A then sythesis the whole chip, timing is perfect. Can anyone gave a clue or pointing me a...

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