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The following code is an IO data flow controller for to and from sram and FPGA.
entity dataflow_control is
state_enable : in std_logic;
output_enable : in std_logic;
camera_clk : in std_logic;
Hi Guys I have been developing code for better part of the last couple of months as well I only learned VHDL in the last couple of months to connect a omnivision 0v5620 to fpga controlled by a pic (for the sccb of the camera) and connected to sram.
I have basically tried everything but my code...
simple vhdl sram code
Hi , Can anyone be so kind to give me some very simple sram vhdl to test my sram chip, I have been writing code for two weeks while thinking my sram is working just to realize that im not actually reading from the sram but from the last info in the data register.
Hi I wrote some code for i2c and it works great write up to the point where i need to read information.
The following code will start with start command >> address(read) >> command of register of interest >> another start command >> address(write) >> actuall reading of the register >> finally...
I have a pruning issue:
if I have the folowing as output
(293) sda_out <= '0' when reset = '1' else sda when rising_edge(sccbclk_inv);
Iget this warning which screws up my program
W CL169 Pruning Register sda_out_cl_2 sccb.vhd (293) sccb_write.srr (23) 14:45:14 Thu Apr 22 compilerReport...
HI Guys, I would like to know, will it be easier to interface ie read/write to an usb flash drive with the aid of a ftdi usb driver off coarse ;). Or write your own nand flash interface.
Also has anyone been able to read/write to and from a flash drive/pen drive or what ever the kids are...
Hi Basic question, I have counter that generates a 400khz clock but I want both a normal an inverted clock. How can I do it. Code is below:
if reset = '1' then
sccbclk <= '0';
sccb_div <= "1100011";
elsif rising_edge(clk) then
if sccb_div =...
Basic I2C, Need help
Hi I have written a I2C interface (I am actually busy interfacing a omnivision ov5620 camera, but im testing the sccb code on a simpler sensor ) in vhdl, for a little temperature sensor. I generate the clock for the scl by using parallel to serial converters clocking out...
Hi I need some help understanding baseband generation.
Can someone briefly explain this or point me into a general direction.
I am building apayload data handeler and camera system for a nano satellite and data stored on my flash needs to be "converted" to baseband I and Q for transmission. I...
Counter help needed
I get latches in my synplify because the following counter is not created with a clock. I have tried to use the conventional clock with an enable to generate a counter as described here, but it still doesn't work. It works in pre synth but latches up in post synth. Can some...
Hi, Guys i have a little latch up issue somewhere below which i cant seem to resolve pls help.
As im very new to vhdl dont judge :)...
process(state_reg, nand_opr, nand_rdy, data_mem, data_in, data_in_reg, data_out_reg) --sensitivity list
I would like to know if its possible to consider a Nand flash memory as one big block, to give it a start address and to consecutively write to the device and then to give it an end address to stop. Instead of writing to every block/page on a diffrent address.
Does anyone know of any nand flash ONFI vdhl code, or does anyone have any experiance in interfacing nand flash to fpga's without using an ip core.
For my masters project i need to build a camera system for a small satellite for remote E observation. I need to interface a camera...