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  1. R

    help! me out of the warning

    If you want a latch to be synthesized: if sync_counter = 100 then if sync_edge_count = 0 then fram_send_slot0 <= X"E000"; elsif sync_edge_count = 1 then fram_send_slot0 <= X"E000"; else fram_send_slot0 <= X"C000"; end if; else fram_send_slot0 <=...
  2. R

    Stupid Encounter scripting problem..

    Encounter uses TCL as his interface langauage: the you can use source <script_path> to execute a script, set <variable name> <variable value> to set a variable, and so on...
  3. R

    How to be a good project lead?

    Hi jordan76, Dilbert is a daily comic (by Scott Adams) about an office worker's struggles in the corporate world... look at "www.dilbert.com"... Regards, R.
  4. R

    Design Verification question

    I'm talking of functional correctness: in this field, the matter is the vectors choice... a functional coverage tool can help you to choose input patterns that involve virtually all expected outputs from your block...
  5. R

    Whats the difference between clock buffering and CTS..?

    CTS = clock trees synthesys Clock tree = a structure for clock buffering Each flop in your design must receive (and sense) clock input at the right instant, to ensure correct output (i.e. no timing violations): then you need to control your edges and your skew on clock lines... Clock analysis...
  6. R

    Help me fix my booth multiplier program

    Re: booth multiplier More info, please! When the multiplier works well, and when not? examine your inputs sequence in both cases and you could find a solution...
  7. R

    how to do ECO? where can I find doc for it?

    To simplify an eventual ECO process, I'll suggest to ever insert some spare cells in any design... so the ECO could be a simple re-routing of your chip, and not a total re-synthesis...
  8. R

    Muxed clocks Problem during synthesis using DC

    Case 3 is equivalent to case 1: while in case 2 all paths (12 MHz paths too) were clocked at high frequency (and the size willl increase), in case 3 only the paths originally clocked at 500 MHz will be at 500 MHz (it's a case analisys, but her effect is limited to the MUX and his logic cone)...
  9. R

    Design Verification question

    I'm adding a little note: You can generate the expected outputs vector from a high abstraction level behavioral model of your chip; using a functional coverage tool, you can create an outputs vector which ensures totally the chip logic correct work...
  10. R

    Problem with function and timing in PAD

    Re: pad, timing, function??? With notimingcheck option, you've deactivated timing checks on internal gates (i.e. setup, hold, ..), but the buffer effect still remains: your clock enters the chip a delta later than using a simple wire... you could verify if any path from stimuli (other than...
  11. R

    Please check if my code is working properly

    Re: copy partial variable Yes, it's good, but dir0 will be the 2nd bit of shift and data0 will be last 5 bits of shift only when posi =0 and shift(0)=0... If this is your expected result, you're ok!
  12. R

    How to simulate & measure power consumption and current.

    Re: How to simulate & measure power consumption and curr See your previous post, I've replied there... you performed an analog simulation, if I well understood... I don't know if you have a digital cells library, but you can maybe try to build a similar library starting from your analog...
  13. R

    Current in digital circuits

    You could use a Synopsis tool named PrimePower to perform a current consumption estimate for your circuit (if your library is well characterized). See the Primepower manual to further infos...
  14. R

    Help! My error: Found logic contention at 40ns on node 'D0'

    found logic contention What it happens in your simulation at 40 ns? maybe the reset release? in your code branch, D and A outputs are'nt set to high impedance state: this could lead to a bus contention with your A and D testbench inputs! An inout port cannot be driven from two signals at the...
  15. R

    [vhdl ] how to deal with unused state in FSM? thank!!

    The unwanted states of a state machine can EVER occur (even if you use a case structure), due to signal glitchs, various mismatchs, etc etc... The problem is: if your state machine goes in an unwanted state, what happens after? the machine can recover from this condition? A good coding...
  16. R

    sdf annotation simulation question

    sdf simulation Your sdf file comes from a post-layout parasitic extraction? It isn't too strange to find some violation in final post-layout simulation: the only possible tip is to make more robust as possible your sinthesys process! Use ever timing constraints worst than needed: so your...
  17. R

    Synthesis problem as constant is expected as the index!

    Re: Synthesis problem Sorry, my solution was already posted in another post... I've deleted it -- Modified by the author
  18. R

    user defined functions in VHDL

    The problem here is the matching between actual and formal parameters: you defined xfrom, xto and xdata (formal parameters) as signals, while the actual parameters you're using are constants. You can: 1) define three signals A, B as integer, C as std_logic_vector and use them to pass actual...
  19. R

    GERBER Basic and its format

    You can download it from:
  20. R

    math division operation in vhdl

    division operator in vhdl For synthesis, you should implement your divider by multiple substraction loops. You can find a related example (with code and testbench) at this url: <http://www.kip.uni-heidelberg.de/ti/TRD/alu/arraydiv/> If you are working in a Synopsys environment. you can use...

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