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  1. S

    IC validation and characterisation engineer

    Pepillo: £12k is pretty low for a university graduate. This would equate to a UK universities PhD student's stipends. Depending on your location where you will be based at, in big cities like London and Birmingham (and more costly in the Southern part of England), you need to spend £2k to £3k...
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    Working culture within intel

    Hello: I welcome your inputs on working culture inside Intel. What is pro and con of the rank and file scheme (also known as R & R)? Given other alternative, would you join this world biggest semiconductor for your career development. I really appreciate your sincere and unbiased...
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    intel freezed all new hiring?

    hi, can anyone comment on this? My lady friend succeeded in the job interview and had been convinced by the hiring manager that she is interested in getting her service in her newly established team. Then few weeks' later (lately), the hiring manager called and told her that she needs her to...
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    dynamic VHDL PCI-core testbench....or anything...

    vhdl pci Do take a look at the following documents. **broken link removed** https://ntserv1.ida.ing.tu-bs.de/EGSE/pci_64_docu/altera/ug_pcitestbench.pdf
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    Cadence Tools - Which Linux do you advise???

    I highly recommended that you use Redhat Linux Enterprise 3.0 as your LINUX OS. regards, Saho
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    Installing LINUX Distribution updates files

    Hello Linux PlayMate: I have a question, in fact, a trivial one. Not sure where to start. Hope you can give me a few spare time of yours; guiding me through the process of updating my Linux laptop. Let's start. I have a laptop installed with SUSE 9.1 pro from the official disk. I am...
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    ModelSIM User Conference 2005 Presentation Slides (PDFs)

    Follow the URL link **broken link removed** regards, Siew
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    Is ModelSim able to take the benefit of multi-processor?

    ModelSIM is a single kernel application. Thus, it only uses 1 processor. But, if you have both licenses for ModelSIM PE and SE, you should be able to run both ModelSIM application (one must be SE, and the other MUST be PE). SAHO
  9. S

    How to extract signal to start or stop dumping

    modelsim + disable dumping Hello. Let me suggest a solution. I have learned that Novas (certainly latest version Debussy and possibly Verdi) does support extraction of sub-signal waveform from a large waveform log. The trick is it is a FSDB formatted file. Luckily, Novas has kindly provided...
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    Which one is better Vera or Specman?

    vera e-specman Hello Again: Ya, as pointed by Aji, I have posted a subject "Seeking TRUTH: Specman Elite" at Janick Bergeron's Verification Guild. Got some replies, even 1 from Verisity representative. Now, about support for Specman Elite, I believe these companies support/back Specman Elite...
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    Which one is better Vera or Specman?

    different specman execution phases I love Specman. It is very very much like VHDL, with few but powerful cosmetics. Given the choice, I will be pick Specman E language, which is adopted as IEEE verification language. Do a search and you will find the official page. Vera? I think it is...
  12. S

    Baseline LDV5 VS ISR Vs QSR

    how about "overlay" of cadence software? is this patch to the baseline installed software? please comment. saho
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    What's the best way to do Regression Testing?

    hello. can someone post example of scripts for reference and coding style. saho
  14. S

    one ppt file about what is modelsim6.0 update.

    Hello Again: When you have spare time, can you scan them and post online? Keep posting any new Mentor Graphics/Model Technology's ppt. Appreciate your sharing attitude. Salute.
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    one ppt file about what is modelsim6.0 update.

    Can you post mentor's tool powerpoint and training workbook as well? Do you have any assertion based tool's user manual or powerpoint? Please share and appreciate your effort.
  16. S

    Assertion based methodology and tool user manual

    hello. I am interested in learning and using assertion (PSL, SystemVerilog) on my next verification project. Can you share with me your success story (not from tool vendor!)
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    FPGA Advantage with Node locked Licence without network conn

    Re: FPGA Advantage with Node locked Licence without network use your hard disk host=disk_serial_num (not sure about the correct syntax, double check, your home work)=???? Check Flexlm user manual (perform a search). Or, give your laptop a flex-id (may requires installation of flex-id...
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    What is Equivalence Checking?

    in addition to the above posting, please visit the site It is about Writing Testbenches: HDL verification by Janick Bergeron. In this post, there are materials on verification tools. I think it could be more precise than my descripton give above. happy learning.
  19. S

    What is Equivalence Checking?

    equivalence checking <=> model checking. it finds its application in comparing RTL vs RTL, RTL vs gate, gate vs gate after design changes (or more kinkily known as ECO, engineering change order). It helps designers by ensuring a minor design changes do not modify other modules's functionality...
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    SystemC will die? Why, can anybody give an explain?

    i don't think so. SystemC will be for System level modelling (transactional level model) and synthesis (Forte Design's Cynthesizer, Coware, Mentor Graphics). Sounds like to the evolution path that VHDL went through. as you know, VHDL had initially designed for simulation. SystemC simulation...

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