Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
To correct the duty cycle of a 5GHz clock, I come up with the attached circuit.
For 5GHz clock, R=10K and C=100fF.
It works almost perfect according to simulation. But I just kind of worried, is there any issue associate with this scheme I have ignored?
Hey ,guys, I got a task to built a verilog HDL (not veriloga) model for a SERDES AFE. This model will be provided for our digital guys to simulate.
Anybody ever do this job? Would you plz show me the general procedure?
3.3v to 5v ic
I'm afraid you might took pranam77 by mistake. I think what he suggest is to use 5V vdd for analog part and then shift down to supply 3.3 digital.
Another solution might use charge pump to boost vdd, but that will be costly and the 5V supply noise will be terrible if not proper...
on chip resistance
Generally speaking, there's high poly resistor (r***_sab) available. Their sheet resistor are about 1Know Ohm/square. Then hundreds of K Ohm will be reasonable.
All in all, you have to check the sheet resistance of all the resistors available first.
My environment is IC5.10.41.
I found it difficult to control the annotate status of the schematic.
Occasionally it displays the right annotations as my choice, but most often it just annotate the Node voltage and can't be reset...
Any good ideas?
I am designing a second order sigma_delta modulator for audio application.
The input frequency is 8kHz and the sampling rate is 1MHz.
The design target is 16bit but he simulated 3rd distortion of the SDM is as high as -54dB.
The slew rate of the first OTA designed to be 20V/µs.
What might is...
Hi, I want to buit a high speed Duty cycle corrector circuit.
The process is 0.18um CMOS.
The highest input and output clock frequency can be as high as 4GHz.
On wafer probe test will be chosen.
But I have no I idea how to built the I/O circuit.
Can I just get rid of the ESD circuit or which...
Paul Brokaw formulated the following practical rule: if on the circuit diagram one can draw a closed line around the supply bus that crosses only drains of MOS devices or collectors of bipolar transistors, then such circuit has the second stable condition when all components are off ...