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  1. DZC

    Is there any issue with this circuit?

    To correct the duty cycle of a 5GHz clock, I come up with the attached circuit. For 5GHz clock, R=10K and C=100fF. It works almost perfect according to simulation. But I just kind of worried, is there any issue associate with this scheme I have ignored?
  2. DZC

    small and large signal difference

    To my understanding, large signal is kind of transfer function when you apply a slow enough signal small signal is around some specific point such large signal transfer function
  3. DZC

    question about threshold voltage in 90nm technology

    I doubt what you've checked is corner related paprameter? Do a simple .OP or .DC in hsipce and check the log file to get the real vth Good luck!
  4. DZC

    How to model a SERDES analog PHY with verilog?

    Hey ,guys, I got a task to built a verilog HDL (not veriloga) model for a SERDES AFE. This model will be provided for our digital guys to simulate. Anybody ever do this job? Would you plz show me the general procedure?
  5. DZC

    how to collect 3.3v to 5v inside chip?

    3.3v to 5v ic I'm afraid you might took pranam77 by mistake. I think what he suggest is to use 5V vdd for analog part and then shift down to supply 3.3 digital. Another solution might use charge pump to boost vdd, but that will be costly and the 5V supply noise will be terrible if not proper...
  6. DZC

    Is 1k ohm for an on-chip resistor a large value?

    on chip resistance Generally speaking, there's high poly resistor (r***_sab) available. Their sheet resistor are about 1Know Ohm/square. Then hundreds of K Ohm will be reasonable. All in all, you have to check the sheet resistance of all the resistors available first.
  7. DZC

    Problem with annotating in Spectre?

    spectre annotate My environment is IC5.10.41. I found it difficult to control the annotate status of the schematic. Occasionally it displays the right annotations as my choice, but most often it just annotate the Node voltage and can't be reset... Any good ideas?
  8. DZC

    How to modeling a SATA cable, plz?

    sata cable simulation I have the SATA RX and TX circuitm, and now I'd like to have a far end loop back test simulation. But I have no idea how to model the channel. Any suggestion?
  9. DZC

    How to implement a PLL lock detector?

    pll lock detector Is there any common used method?
  10. DZC

    How can I deal with 3rd HD in a 2nd SigmaDelta Modulator,plz

    I am designing a second order sigma_delta modulator for audio application. The input frequency is 8kHz and the sampling rate is 1MHz. The design target is 16bit but he simulated 3rd distortion of the SDM is as high as -54dB. The slew rate of the first OTA designed to be 20V/µs. What might is...
  11. DZC

    technology features for 0.13u- High Voltage PDK,MMRF PDK

    technology features You have to specify a exact process. To put them in a single PDK may make you even confused...
  12. DZC

    difference between CML and CMOS

    For higher frequencies (>GHz) CML's power dissapation may be comparable or even less than CMOS.
  13. DZC

    How to realize on-wafer test for a 4GHz clock?

    Hi, I want to buit a high speed Duty cycle corrector circuit. The process is 0.18um CMOS. The highest input and output clock frequency can be as high as 4GHz. On wafer probe test will be chosen. But I have no I idea how to built the I/O circuit. Can I just get rid of the ESD circuit or which...
  14. DZC

    A question on start-up circuit in biasing circuit, plz

    Paul Brokaw formulated the following practical rule: if on the circuit diagram one can draw a closed line around the supply bus that crosses only drains of MOS devices or collectors of bipolar transistors, then such circuit has the second stable condition when all components are off [106]...
  15. DZC

    Low Power Pipeline ADC

    This question is too general...
  16. DZC

    difference between thick gate and thin gate device

    thick gate=>low Vth,low breakdown voltage,high speed thin gate=>on the contrary
  17. DZC

    Offset of the operational amplifier, how can it be reduced

    It might depend on your application. chopped,capacitor coupling at the input and output will do.
  18. DZC

    How to set the rise time for a step signal in matlab

    caculate the slope and use a "saturation" followed?

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