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    Need a solution for Vin 1.8 to 12V , and vout~4.2V

    I have a power system need to design. It input voltage down to 1.8V and up to 12V; DC but often varies with time. Output Voltage is near 4.2V, Iout~600mA I search for TI; they have a buck/boost converter TPS55065-Q1. But it is very complicated than I needed. Has there other simple method to do...
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    Question of razavi's book (chapter 13 mismatch)

    Hi The equations (13.57)~(13.59) of razavi’s book at pp. 464 The result is that mismatch is inversely proportion to (n)^1/2. How to derive from eq 13.57 to eq 13.59? Thanks ~ !!
  3. C

    error amp of current mode buck converter

    buck converter current mode Hi ~~ The system bandwidth of buck converter often set : 1/10*clock Frequency . But the error amp spec only identifies Gm Av. How about the bandwidth , slew rate ?? Do we need a very fast slew rate of error amp? Or if slew rate too fast ,the system intends to...
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    nwell resistor junction leakage ?

    junction leakage Hi ~! If i have a resistor formed by nwell/P-sub structure, what is the junction leakage current about this resistor ? I have to know it because i have a very small current near 50nA need to pass a large nwell resistor about 3um*3300um. Thanks ~ !!!
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    question about psrr simulation

    psrr simulation Hi ~ i have an LDO regulator. and i simulate it psrr. i found it crossover 0db at about 90kHz (max +14dB). but if i use a 10mV 90kHz sin wave , the output have only 6mV sin wave , equal -4.4dB. what result is meaningful ?
  6. C

    model parameter of nmos drain to substrate leakage current ?

    Hi ~ Is any one know the parameter of nmos drain to sub reverse current (or say pn junction leakage current) in spice level 49 model ? Thanks ~ !
  7. C

    mos corner question - is the sf and fs corner possible ?

    mos coner we often say mos has tt ss ff sf fs corners. the s corner due to think tox and f corner refer to thin tox process, then vth will be larger or smaller. The oxide of pmos and nmos are processed in the same time. So the sf and fs corner is possible?? thanks ~ !!
  8. C

    reference for low power constant current biasing circuit ?

    Hi ~~ Dose anybody have papers or any related book for very low power (supply current near nano A) constant current biasing circuit ? thanks !
  9. C

    Question about simulation ICMR (input common mode range)

    icmr input common mode range Hi ~~ If I have a two stage single ended differential amp, and the input is rail to rail (has NMOS & PMOS as input stage), but output is cascode configuration (two nmos cascode & two pmos cascode). When simulation ICMR we often use unit gain configuration, connect...
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    opamp simulation question (Vos & PSRR & CMRR)

    cmrr op amp Hi~~~~ If i have a single ended opamp, i want to simulation it offset voltage. I often see the simulation step is that Vin+ & Vin- tied to ground and measure output voltage, the output voltage/Gain is the Vos. But when input of opamp is NMOS transistor and single voltage supply, it...
  11. C

    How to measurement Gm of OTA?

    Hi ~! Is anybody know how to measure the real Gm(≡Iout/Vin) versus frequency of OTA? (not simulation is measurement) thanks a lot !
  12. C

    Question about Sansen’s book (analog design essential)

    This slide is at sansen's book pp.23 slide0141. The author said that the corresponding gm/Ids is 4.2 (1/V) But in my calculation the value is about ~ 9.43 (1/V), approximately the same as his previous derivation. Could anyone tell me why? Thanks a lot ~~!!
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    How to measure Rds(on) Power NMOs?

    Hi ~~ I have a Power MOSFET, and want to measure it Rds(on). but there are many method to measure it, could any body can tell me a easy and precision method to measure it! thanks ~!!
  14. C

    How to see current phase in hspice

    Hi~~~ is anybody know how to see current phase in hspice i only find .print vp(node) , it can only see the voltage phase thanks a lot !
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    How to determine the error amplifier’s gain and unit gain frequency for a LDO design?

    How to determine the error amplifier’s gain and unit gain frequency for a LDO design? Hi~~ This is my first time to design a LDO. I have seen some theses about it. But i have some questions about that: How to determine the error amplifier’s gain & unit gain frequency? How much it is? And how...
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    Bandgap reference transient analysis

    Hi ~~ I have a question about bandgap reference Like attached picture This is my transient analysis result (simulate vdd off and on conditions) Why the bandgap voltage overshoot is so large? (regardless there has start up circuit or not……) My opamp is well designed. (gain 80dB, phaseMargin 70...
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    How to determonie the opa specs for bandgap reference?

    Hi all ~ i have a question about how to determine the unit gain bandwidth, gain,slew rate ....of OPA for bandgap reference. thanks a lot ~!!
  18. C

    how to change crystal oscillator frequency?

    Hi~~ i want to generate a 1.28MHz clock frequency. So i use this crystal oscillator https://www.txc.com.tw/download/o/ocxo_dip.pdf in pdf , it say the avalible frequency is 5~70MHz I want to generate a 5.12MHz frequency then divide 4 = 1.28MHz but how should i design circuit then the crystal can...
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    how to transfer voltage level

    Hi~~ i have a bettary voltage 0~6V how could i transfer 0~6V to -3~ +3V ? thanks a lot~~
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    Good book for cmos op amp

    op amp layout Hi~~~ except for razavi,allen & gray Does some one know other good books for cmos op amp design? or any good thesis? thanks a lot~~!

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