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    I'm open sourcing the instruction set of my CPU

    I'm open sourcing the instruction set of my cpu. The ISA is a vliw/risc hybrid, where the "small" instructions are variable width, packed in a bundle. They do not cross a bundle. Sizes multiples of 16-bit, last 16 bit of a 256-bit bundle are "stop" bits for each instruction. This is to ease...
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    placing and routing custom memory cells

    Is it possible to custom design a memory cell for e.g. multi ported register file or multi-ported reservation station and have place and route tools build a memory out of it by importing it in Verilog? The said "cells" will have multiple inputs and outputs and consume a lot of wire.
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    Project for high performance CPU with OSS friendly firmware

    Heptane - This is a project for a high-performance 9-issue VLIW-like processor, but with out-of-order execution. It will feature a x86_64 binary translation. The translator and firmware will have OSS (LGPL) versions released. Unlike previous attempts at binary translating CPUs, which had only 2...
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    Multi-port register file in HDL

    q1: Do place and route tools synthesize multi-port register files with "write-first" read-during-write behaviour or are they restricted to only "undefined" read-during-write? q2: In a super-scalar cpu would the multi-ported register files be synthesised ok by place-and-route tools or a...
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    Usage of posedge and negedge flip flops in same design

    Is it OK to use both positive and negative edge flip flops on the same clock in the same design from perspective of place & route tools? Is it going to make timing analysis impossible? Note that it won't have combinational logic depending on the outputs of both a posedge and a negedge sensitive...
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    ASIC memory compilers

    do memory compilers support bit (and/or byte) enable? do they support asynchronous read?
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    arrangement of data bits in reservation stations by place and route tools

    I'm currently developing a cpu with ooo execution. I was wandering how would place and route tools arrange the data bits in the reservation stations. Will it be 1)a0a1a2... b0b1b2... or 2) a0b0a1b1a2b2... ?

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