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I agree your description above.
However, for project timing sign off condition. Is it necessary to take Typical corner as one sign off condition, if the foundry just recommend to do worst/best, worst LT/best HT as sign off condition?
we have schematic , but now we want to implement it using SE .
So , could we transfer schematic in cds5.0 to verilog netlist . so that we can use foundry's library to PR our product.
Please help , thanks a lot!
SE or Apollo
I now find the constraint file format is not same for SE and Astro.
SE is using GCF which was created by cadence few years ago.
Astro may use SDC for its own constraint format.
sigh~! I begin to feel that i could not keep the pace of the developing of EDA tools!
So , system...
But ,is there any compatiblity between GCF and SDC?
And i have noticed that SDC is the timing constraints from synopsys design compiler. If it is true, that means cadence will use synopsys constraint file format in its product : Encounter?
Re: SE or Apollo
To me, the essential of SE is to write a good constraint GCF file.
Almost the rest parts could sustained from foundry, but GCF is definite constraint to your design.
BTW, how could we write a perfect GCF constraint file?
Dear Kxchorus, thanks for your attention.
1. set to 80%
2. yes I made WRoute.Timing.Driven True
3. Not yet, i want to know how?
4. I have pass CTS, no timing violations this time.
And now , I found the IO of STD cell is not located on the cross point of grid line. Is it affect routing ? and...
Hi Folks, i am a rookie for using SE. There is a problem I could NOT solve for few weeks.
I could NOT make my design finish routing . I have reduce the ROW Utilization , increase the distance between IO and Core. But it still doesn't work.
That made me very depressed.
Is there any good advice...