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I am building a PCIE EP using Ultrascale PCIe IP from Xilinx. I am using 2017.3 Vivado for the design.
Since the ultrascale EP supports only AXI Stream, I need a converter from AXI4 to AXIS, I went through some of the forums and read that people could use AXI-DMA or AXI-Datamover IP to...
I am having issues trying to simulate the PIO example using the below command which was mentioned in the pg156 manual for ultrascale_pcie_gen_3 from Xilinx.
demo_tb.exe -gui -view wave.wcfg -wdb wave_isim -tclbatch isim_cmd.tcl -testplusarg TESTNAME=sample_smoke_test0
I am able to see the...
well I need to decide between 2 job opportunities. One is that of a Senior CAE Engineer and the other is a FPGA Firmware development engineer. I am aware of the roles and responsibilities of both the positions. Well I am not able to decide which job would enhance my career.
I am trying to portmap a signal using WHEN command.
for example in the code below
x => '1',
a => (b when (x='0') else c),
y => x"0"
I get the below error during compilation
am I right in using the WHEN command?? How am I supposed to change the code reading that...
This is not a technical question. I am interested in improving my knowledge on High Speed Digital Communication Systems (LVDS, high speed interfaces design in FPGA), could you guys suggest or recommend me some links where I can read and also try to design them on FPGAs. I am focussing...
I am implemented an real time image correction in an Arria Altera FPGA. However I have this problem with the timing violations. I have used about 95% of the logic available in the FPGA. Before the implementation of this correction mechanism I had about 89% logic utilization. My logic...
I have generated a new .sopc file from Qsys. I am trying to compile my nios project but have these errors. Do you guys have experienced such errors??
The errors are:
make:*** [-recurs-make-lib] Error 2
make: *** [newlib] Error 1
In my qsys project I have added new custom...
I have attached a simulation screenshot of my VHDL program. The output data is 0 in the beginning and is not synchronous with input. I am using a ROM as LUT which is initialised with my .mif file. While I am not able to sync the output (data_out) and input (data_in), the end output...
I have attached a screenshot of the image obtained from a CMOS Image Sensor. Could any of you guys tell me as to why do I get such pattern (column like)?? Do any of you guys experienced such an image?? I do not think its fixed pattern noise effect from the image sensor.
I have a general question regarding Jitter issues and problems. The old circuit consisted of a 25Mhz crystal clock oscillator. The 25Mhz clk was increased to 125Mhz clk and given to the transmitter of the FPGA. However there are jitter issues in the circuit and the jitter needs to be...
I am trying to load my Altera Arria - II FPGA with the .sof file generated. The loading is successful but the FPGA LEDs do not turn ON/blink. When I program the FPGA with an old .sof file it works. My question is can u tell me as to why does this happen??
Before programming the .sof...
I am using arria II GX : EP2AGX45DF29I3 fpga in my porject. I referred the datasheet of arria II GX and saw the transceiver jitter performances of the GX series fpga's for different protocols. However I could not find jitter performance for protocol "Basic" at a datarate of 6.275 Gbps...
I have written a VHDL program to use ROM as look up table. The program compilation is done without any errors. However during simulation (screenshot is attached below) I get initialization problems where data_out values are read as 000 ans 3FF (hexadecimal values).
Since I have given...
I am trying to find a maxima using a 8 neighborhood pixel for an filtered image. It is basically a 2D filter moving along the pixels of the image from left to right. I am trying to implement the same using VHDL. I have few questions regarding the approach.
1. When I read the pixels in...
Is there a CMOS camera chip available in the market which gives difference of two successive frames??
I found a IEEE paper regarding the design of such a chip.I wanted to know if there are any IC's in the market which does this work??
I am not able to read the desired output of a signal from the fpga in the ILA waveform.I have connected one of the probe to the signal.I am reading junk values.Could you tell me what could be the reason why I am getting junk values for a 14 bit wide signal..Its showing as "3FFF" as in...
I am using ILA to observe the output given out by my fpga.However there is an option to write down the data observed into a .csv file by giving the command in tcl.
I had set the sample depth to about 131072 in the ILA so that I could see the data(i.e in my case pixels of an image)...
I am using ILA from the xilinx coregen,the behav simulation results are fine.Synthesis,implementation,bitstream generation are finished but however I cannot see the data coming from ila.Could you tell me where am i going wrong?
I looked for answers regarding few errors in the xilinx...
I am designing a filter to do convolution of a binary image which is stored in the bram as a .coe file.I am able to do convolution and my logic is working fine.Well since images are 2d I need to do filtering in the horizontal direction(x direction) and also in the vertical direction(y...