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  1. K

    Confused with Q factor calculation of pi match in Thomas Lee's RFIC book chapter 3

    In Thomas Lee's RFIC book chapter 3 page 97, he gives an equation Qtot = Qleft + Qright for pi-match network。 However in book Electromagnetics for High-Speed Analog and Digital Communication Circuits by ali m. niknejad chapter 7.3 page 196,he gives an equation Qtot = (Q1 + Q2)/2。 There is a...
  2. K

    Moved]: how to calculate jitter when simulating the PLL

    I have a question. What's the authentic method to quantify the jitter when simulating the PLL used as a clock. I've tried two ways. First, do the transient simulation and use the eye diagram function in cadence to see the peak-to-peak jitter. As for this method, is the transient noise...
  3. K

    phase noise to jitter convertion

    As for a free-run oscillator, the jitter accumulates over time. The wavescope calculates jitter in a certain time windows. My question is if I want to know the rms jitter of a oscillator in a time range of ,maybe 4us , then what the is the frequency range for the integral of phase noise in...
  4. K

    [Moved]: jitter influence on TDC

    Can anyone give some information about this topic? background : The TDC is for 3-D radar for time measurement using a simple counter based structure. question1 : If the clock is from a vco, will the jitter accumution affect the final results? If yes, then how much difference will it lead...
  5. K

    Error when running VCS

    I'm running the simulation by VCS on my own mechine, but there are error when doing ./simv -gui as shown in picture. And the inter.vpd file isn't generated. Could anyone tell me how to do? Thanks~
  6. K

    About high frequency signal drive

    Thank you, but some puzzles about your reply. As the receiver end is an inverter, how to estimation the impedance, do you mean the small signal impedance? This line transmits square wave as a clock. - - - Updated - - - Thank you, I've done shield to put ground line between this...
  7. K

    About high frequency signal drive

    I am dealing with a 6.4mm2x6.4mm2 array chip, and there is a long high frequency signal line in the chip(about 180MHz, 1um wide ,3.2mm long ,and made of top metal). I want to know if this metal line is ok for the signal transfor, would the signal attenuation happen? If true, how can I consider...
  8. K

    [Moved]: about jitter accumulation

    For a VCO alone, the jitter is accumulated as the time goes, but a PLL don't, is this right? if right, then i want to know if a Frequency Locked Loop can null the jitter accumulation? (FLL is something like PLL,and its input and output signals are frequency, so the transfor function for the...
  9. K

    About Injection Locked Oscillator

    Following picture are the circuit I wanna test(simple enough), the PSS Pnoise simulation setting and the simulation error. I'm alone with this project and unfamiliar with this topic,can you show me where i was wrong and maybe some inscturctions of the circuit? Thank you very much
  10. K

    About Injection Locked Oscillator

    I need a 200MHz clock for TDC provided by ring VCO, but considering jitter accumulation conventional ring VCO doesn't fit. I want to design a injection locked ring oscillator, but can't find some proper paper. Can any one help me with some paper name? Another question is how to simulate phase...
  11. K

    How to explain jitter accumulation

    As for a single VCO, output clock wave is far more different from the wanted when the test time grows.can this call jitter accumulation? if not ,what is the real performance of jitter accumulation? As I found, PLL and DLL can reset jitter accumulation whereas VCO can't ,why ? Thank you for...
  12. K

    How to design a low jitter clock generation circuit

    Thank you. As I know, LC oscillator is good,but mainly for communication IC circuit. If I design a PLL for system clock, is this enough with ring VCO? If it's enough, how can I get better jitter performance for further improvment. Thanks.
  13. K

    How to design a low jitter clock generation circuit

    Recently,I've found some delay structures for low jitter use. For example, positive feedback or latch to speed up the voltage rising or falling, full swing without tail current source and ...... This is for improving VCO jitter performance, but I want to konw if there is any system level...
  14. K

    How to design a low jitter clock generation circuit

    I want to do a project about low jitter clock generation for SOC or ADC use.The main idea is to do PLL. Is there any suitable structure for low jitter performance? For example,can Sigma-Delta work for this particular use? In addition, the PLL is based on ring VCO for we use CMOS digital...
  15. K

    [SOLVED] How to simulate a ring VCO using HSPICE

    I've tried PWL voltage source on VDD,still doesn't work. I add a control command .option accurate=1 ,then it work. Thank you anyway .
  16. K

    [SOLVED] How to simulate a ring VCO using HSPICE

    I'm learning HSPICE. When simulating a ring VCO, I can't get oscillating wave. It seems to be locked,but i'm sure the connection is right for the netlist is available on Cadence Spectre. Is there any issues. Thanks in advance.

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