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  1. R

    Angstrom Design Automation DECIMM ESD software

    Anyone used or tried out DECIMM ESD simulation software? www.angstromda.com Got no reply last time I asked but that was some years ago.
  2. R

    nwell proximity effect on nmos Vth

    If you are using a dual well process, then where there isn't Nwell (or Native) you will have Pwell implant. Near the edges of Pwell you will get wpe effects.
  3. R

    n+/psub (native) ESD diodes

    OK thanks. In ESD Symposium 2002 paper "Optimization of Input Protection Diode for High Speed Applications" they found that n+/psub diodes were indistinguishable from n+/Pwell diodes at high injection but they did highlightlight other issues.
  4. R

    n+/psub (native) ESD diodes

    Typically ESD diodes to ground will be n+ in Pwell, but in a process with native option n+ in psub without the Pwell implant is an alternative. This can have lower junction capacitance so would seem useful for a lower capacitance ESD diode. Are there any disadvantages for these diode types for...
  5. R

    DECSIMM ESD simulation tool

    DECIMM ESD simulation tool Anyone tried this simulation software? About the Book - ESD Design for Analog Circuits Thanks, R (No connection with angstromda) [edit] Just corrected name in title. I'll take the silence as a no...
  6. R

    MOS mismatch vs temperature

    Anyone seen any information about how MOS mismatch changes vs temperature? For a circuit with trimming or calibration this can be important. I found one source which claims matching improves at higher temperature but I would be interested to know if this has been found elsewhere...
  7. R

    information needed on the effect of backbias on mismatch

    Some data from a different for 1.8V nmos from a different 0.18u process. This confirms that increasing backbias increases backbias.
  8. R

    Power Clamp for ESD Chip Protection

    Yes sometimes pmos devices are used. They will need a larger area than nmos for the same ESD current. They are less prone to snapback breakdown which I assume is why they are sometimes preferred.
  9. R

    what's the maximum pratical value for poly resistor

    If you are making a large RC time constant with gate capacitance as the C don't forget that sub 0.18um generation thin oxides can have significant leakage so there will be IR drop across a large R. Got burnt by this when a foundry default model didn't include gate leakage.
  10. R

    Calibre diode parasitic extraction

    bump. I am trying to figure this one out as well. I want to extract Nwells as diodes without having to add them to the schematic.
  11. R

    questions for tsmc 0.18 PDK

    The _mac & _mis are for mismatch modelling. The mismatch in the MOS devices will normally be more significant than bipolar mismatch in a cmos bandgap unless you use auto zero techniques..
  12. R

    information needed on the effect of backbias on mismatch

    Re: mismatch with backbias? Example paper
  13. R

    how to decide the overdrive voltage

    Isn't it the other way round - for a current mirror where you are trying to match current the overdrive should be larger eg 300mV. The other constraint is the voltage headroom for the mirror devices, the larger the overdrive the more volts drain-source you need to keep the devices saturated...
  14. R

    information needed on the effect of backbias on mismatch

    mismatch with backbias? Anyone got any information on the effect of backbias on mismatch? I have a circuit which is varying more than expected. The foundry model doesn't take the effect of backbias on the mismatch, which could be part of the problem. I found a few papers which showed mismatch...
  15. R

    multi-threaded LTspice/intel i7

    LTspice has recently been upgraded to support multiple threads. I've never got round to trying this simulator but will give it a try soon. Mike Engelhardt of Linear Tech says the intel i7 is currently the fastest processor for LTspice - it can be 2x compared to a quad core. Anyone tried the i7...
  16. R

    what's the difference of mim and mom cap?

    what is momcap For deep sub micron (<100nm) with narrow minimum horizontal spacing between metals the interdigitated MOM style caps can be as area efficient as MIM caps but don't need extra process steps.
  17. R

    When to use Poly routing ?

    Was this in a non-volatile memory based on stored charge? In this case I could understand taking extra precautions about leakage but normally I wouldn't expect metal routing to be leaky, or leaky enough to matter.
  18. R

    who ever use fastspice ??

    A friend working on analog/rf IC says good things about this simulator for speed up compared to Spectre. I've have not seen or used it myself so don't know any details.
  19. R

    Which unix shell for Windows?

    In the instructions for the Windows version of Hsim it says Hsim should be called from a unix shell, not a DOS command prompt. Which unix shell that can run in a Windows environment would folks recommend for ease of use/installation etc? Thanks, R
  20. R

    Gate length to prevent hot electron transistor shifts

    I tracked down some data for a 0.35um cmos process: For Vds =< 2.5V minimum gate length is fine. For Vds =< 3.6V nmos gate length should be 1um & pmos 1.7um (for worst case Vgs = 0.5 Vds) Really I am after 0.25u information but this gives some idea.

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