Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
OK thanks. In ESD Symposium 2002 paper "Optimization of Input Protection Diode for High Speed Applications" they found that n+/psub diodes were indistinguishable
from n+/Pwell diodes at high injection but they did highlightlight other issues.
Typically ESD diodes to ground will be n+ in Pwell, but in a process with native option n+ in psub without the Pwell implant is an alternative.
This can have lower junction capacitance so would seem useful for a lower capacitance ESD diode.
Are there any disadvantages for these diode types for...
DECIMM ESD simulation tool
Anyone tried this simulation software?
About the Book - ESD Design for Analog Circuits
(No connection with angstromda)
 Just corrected name in title.
I'll take the silence as a no...
Anyone seen any information about how MOS mismatch changes vs temperature?
For a circuit with trimming or calibration this can be important.
I found one source which claims matching improves at higher temperature but I would be interested to know if this has been found elsewhere...
If you are making a large RC time constant with gate capacitance as the C don't forget that sub 0.18um generation thin oxides can have significant leakage so there will be IR drop across a large R. Got burnt by this when a foundry default model didn't include gate leakage.
Isn't it the other way round - for a current mirror where you are trying to match current the overdrive should be larger eg 300mV. The other constraint is the voltage headroom for the mirror devices, the larger the overdrive the more volts drain-source you need to keep the devices saturated...
mismatch with backbias?
Anyone got any information on the effect of backbias on mismatch? I have a circuit which is varying more than expected. The foundry model doesn't take the effect of backbias on the mismatch, which could be part of the problem. I found a few papers which showed mismatch...
LTspice has recently been upgraded to support multiple threads. I've never got round to trying this simulator but will give it a try soon.
Mike Engelhardt of Linear Tech says the intel i7 is currently the fastest processor for LTspice - it can be 2x compared to a quad core.
Anyone tried the i7...
what is momcap
For deep sub micron (<100nm) with narrow minimum horizontal spacing between metals the interdigitated MOM style caps can be as area efficient as MIM caps but don't need extra process steps.
Was this in a non-volatile memory based on stored charge?
In this case I could understand taking extra precautions about leakage but normally I wouldn't expect metal routing to be leaky, or leaky enough to matter.
In the instructions for the Windows version of Hsim it says Hsim should be called from a unix shell, not a DOS command prompt.
Which unix shell that can run in a Windows environment would folks recommend for ease of use/installation etc?
I tracked down some data for a 0.35um cmos process:
For Vds =< 2.5V minimum gate length is fine.
For Vds =< 3.6V nmos gate length should be 1um & pmos 1.7um (for worst case Vgs = 0.5 Vds)
Really I am after 0.25u information but this gives some idea.