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  1. Z

    What CTS method can reduce clock skew in Apollo?

    clock skew in Apollo What CTS method about generated clock & overlapp & gated clock can reduce skew?
  2. Z

    Help me with Chip Implement flow from RTL to GDSII

    Chip Implement flow EDA tools is very complex. Anybody have good idea for Chip Implement flow from RTL to GDSII. I use synopsys flow DC=>PC=>astro (primtime)
  3. Z

    Apllo to CTS for HFN, puge Buff/Inv to cause funtion error

    I use set_ideal_network for HFN in DC. Because some of HFN is general singal (not set,reset) DC will change my structure inserting Buff/Inv. And when I use Apllo to CTS for HFN, puge Buff/Inv to cause funtion error How can I solve it.
  4. Z

    About Cell_based Design flow

    I have one problem. When I use cell_based design flow, I have some macro. When I pre-simulation RTL-code , I can use behavior model for macro. But I want to post-sim for SDF back-annotation, how can I treat it?
  5. Z

    Many online e-books repository

    Many online book https://www.edatoolscafe.com/EDATools/EDAbooks/
  6. Z

    How can I get Model from HardMacro to put it together to sim

    From RTL-cod I can use SDF for backannoation. How can I treat to H.M. to whole Chip ?

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